Vinaya Gudeangadi

Director of Engineering

Bengaluru, Karnataka, India25 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC Physical Design and Front-End Design.
Led multiple successful SoC implementations across industries.
Proven track record in managing cross-functional teams.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in ASIC and SoC implementations.

Contact

Skills

Core Skills

System On A Chip (soc)Physical DesignCpu DesignAsic DesignProcessor EngineeringRtl Design

Other Skills

Project ManagementDesign PlanningPower GatingTiming ClosureGPU ImplementationNetworkingDesign MethodologySynthesisBehavior Model DevelopmentApplication-Specific Integrated Circuits (ASIC)VerilogVery-Large-Scale Integration (VLSI)

About

An ASIC Physical Design expert with a good knowledge of Front-End Design. Physical Design implementation of varieties of CPU/GPU cores.

Experience

25 yrs

Total Experience

3 yrs 1 mo

Average Tenure

7 yrs 6 mos

Current Experience

Intel corporation

2 roles

Director of Engineering

Promoted

May 2025 – Present · 1 yr

Engineering Manager

Nov 2018 – May 2025 · 6 yrs 6 mos

Infineon technologies

SoC Design Lead & Project Management

Sep 2017 – Nov 2018 · 1 yr 2 mos · Bangalore

SoC Implementation for Automotive, Power Management & Consumer applications starting from RTL to GDSII.

System on a Chip (SoC)Project Management

Nxp semiconductors

Engineering Manager

Oct 2015 – Aug 2017 · 1 yr 10 mos · Bangalore, India

Leading the physical design activity in the Media group of Micro-controller organization.
Working on implementation VPU (Video Processing Unit), Display Controller in Samsung-28FDSOI, TSMC-28HPM technology nodes.
Design Planning & Partitioning, Hierarchical P&R implementation,
CPF based low-power implementation (power gating),
Single core ARM Cortex A53 implementation,
Integrating complex analog macros,
Driving the hierarchical timing closure effort,
Working with teams across multiple sites (Bangalore, San Jose, Austin, France)

Physical DesignDesign PlanningPower GatingTiming Closure

Smartplay technologies - an aricent company

Engineering Manager

Oct 2013 – Sep 2015 · 1 yr 11 mos · Bangalore, India

Leading a Smartplay Team at Intel ICF (Intel Custom Foundry)
Working on Tensilica CPU & Imagination GPU Cores.
Implementing the Mali GPU for ARM as technology demonstration.

CPU DesignGPU Implementation

Brocade

Staff ASIC Engineer

Nov 2012 – Oct 2013 · 11 mos · Bangalore, India

Working on the implementation of Brocade networking switches/router chips using IBM 32nm SOI technology.

ASIC DesignNetworking

Lsi corporation

Senior Design Engineer

May 2005 – Nov 2012 · 7 yrs 6 mos · Bangalore, India

Working in the Processor Engineering group on the implementation of ARM single & multi CPU core implementation (Cortex R4, Cortex A9, ARM11).
Working in the design flow methodology team.

Processor EngineeringDesign Methodology

Sanyo semiconductor

Design Engineer

Aug 2003 – Apr 2005 · 1 yr 8 mos · Gifu, Japan

Working on the RTL design of a media processor SoC.
Working on the NAND Flash Interface & LCD Controller.
Synthesis & Pre-layout STA.

RTL DesignSynthesis

Tata elxsi

Design Engineer

Jan 2001 – Jul 2003 · 2 yrs 6 mos · Bangalore, India

RTL Design of SDRAM Controller, NAND Flash i/f, AHB2APB Bridge.
Behavior model development using Verilog/VHDL for SD Card, NAND Flash, NOR Flash, SDRAM.

RTL DesignBehavior Model Development