May 2019 – Dec 2019 · 7 mos · Sunnyvale, CA

• Developed Failsafe Finite-State Machine (FSM) towards Automotive Initiative.
• Project: To make the inferred FSM failsafe in logical synthesis
• Challenges: To prevent Faults translating to Failure in automotive ICs
• Result: With the application of Digital Communication concept of redundancy,
• by turning on a switch, the RTL designer will be able to re-encode the FSM to become Failsafe. (ISO-26262 compliant)
• Impact: The project was one of the key projects in catering Synopsys logic synthesis tool to Automotive IC manufacturer and probing a new domain.

Aug 2016 – Jul 2018 · 1 yr 11 mos · Bengaluru Area, India

• Responsibilities:To enhance correlation between Design Compiler(DC) and Formality, improve DC run-time and fix customer critical issues and quality issues reported by Product Validation(PV) team
• Projects:Handshake signals - guide-constant enhancement and guide-equal-opposite generation in gate-level-optimization engine to improve DC<->Formality correlation. De-prioritization of I/O pathgroup optimization during synthesis to improve DC run-time
• Addressed issues:Extensively worked on timing engine and DRC fixing engine and fixed customer critical issues in a timely manner.Fixed issues in Scenario-management engine and addressed quality issues in DC-optimization engine reported by PV team

Jun 2016 – Jul 2016 · 1 mo · Bengaluru Area, India

• Project: Design and development of RISC based CPU for Tejas aircraft.
• Contribution: Involved in the design of pipeline architecture stages and designed the ALU module in Verilog. Regression testbenches written in System Verilog to extensively test the modules designed.
• Learning: Enhanced knowledge of FPGA design methodology and writing System Verilog Testbenches