Praveen Vadlamudi

Product Manager

Bengaluru, Karnataka, India9 yrs 11 mos experience

Key Highlights

Expert in Physical Design for advanced process nodes.
Proficient in DFT and sign-off flows.
Strong background in VLSI and mixed-signal design.

Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in advanced semiconductor technologies.

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Skills

Core Skills

Physical DesignStatic Timing AnalysisDftLogic Synthesis

Other Skills

Power planningPlacementRoutingVerilogSystem VerilogFormalityConformal LECPhysical verificationFusion compilerStandard cell library QualityStandard Cell Library Quality AnalysisVLSIPythonCadence VirtuosoMixed-Signal IC Design

About

• Worked as Member of Technical Staff in Cores Tool Flow Methodology team to enable Physical Design flow, DFT specification and flow setup , LEC with formality and conformal for all core designs. • Worked on Physical Design (RTL to GDSII ) implementation for intel 4nm, 7nm, 10nm, 14nm and 22nm and TSMC 3nm , 4nm and 5nm. • Worked on Logic Synthesis, Floor planning, Power planning, placement, CTS, routing, fill and all physical design sign off flows • Worked on Low power design closure and associated sign off flows • Worked on Physical verification (DRC/LVS/Antenna.etc) • Worked on Reliability verification (EM/IR drop etc) • Worked on standard cell specification definition for MIG IPs from 22nm to 4nm intel process nodes.

Experience

9 yrs 11 mos

Total Experience

3 yrs 9 mos

Average Tenure

2 yrs 3 mos

Current Experience

Intel corporation

Physical Design Engineer Lead

Mar 2024 – Present · 2 yrs 3 mos · Bengaluru · On-site

Physical DesignStatic Timing AnalysisLogic SynthesisDFTPower planningPlacement+1

Amd

Member of Technical Staff

Sep 2022 – Mar 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India · On-site

Worked in AMD as Member of Technical Staff in CORES Tool Flow Methodology team.
Enable and support Physical Design flow for cores designs and includes below domains and flows.
Synopsys Formality
Cadence Conformal LEC
DFT
Physical Design(PNR)
Extraction
Prime Time

VerilogSystem VerilogDFTPhysical DesignFormalityConformal LEC

Intel corporation

Physical Design Engineer

Jun 2016 – Aug 2022 · 6 yrs 2 mos · Bengaluru Area, India · On-site

Worked with Intel Technology India Pvt Ltd as a Digital Design Engineer, with total 7 years in VLSI industry focusing on Physical Design implementation and sign off flows for Mixed Signal IPs.
Worked on ASIC Physical Design RTL to GDSII implementation flow for 5nm, 7nm, 10nm, 14nm and 22nm.
Worked on Logic Synthesis, Floor planning, Power planning, placement, CTS, routing, fill and all physical design sign off flows
Worked on Low power design closure and associated sign off flows
Worked on Physical verification (DRC/LVS/Antenna.etc)
Worked on Reliability verification (EM/IR drop etc)
Worked on standard cell specification definition for MIG IPs from 22nm to 5nm process nodes.

VerilogSystem VerilogLogic SynthesisPhysical DesignPower planningPlacement+2