Nithin S.R — Software Engineer

• Hands-on in all phases of DFT flow, from RTL till tape-out • Spyglass DFT checks at RTL stage, Coding Spyglass DFT connectivity checks • Scan insertion, Scan DRC debug and DFT test point insertion • Scan compression logic RTL generation (Mentor EDT), synthesis and integration • On Chip Clock controller implementation and insertion • Wrapper chain implementation and X bounding • IJTAG (IEE 1687), Hybrid TK-LBIST and LBIST verification • MBIST insertion (LVMBIST) with BIRA and BISR capabilities • Chip level MBIST integration, BISR integration and verification • Test pattern generation (EDT and SCAN) for SAF, TDF and path-delay fault models • Test coverage analysis, DRC debug and coverage enhancement • Full-chip level ATPG, SDF annotated pattern simulations and failure analysis • Full-chip level MBIST, timing simulations and failure analysis • DFT timing closure support and SDC validation • Manufacturing pattern generation (MBIST and ATPG) and pattern conversion • Automation and flow development for DFT requirements • Verilog coding of designs with complex FSMs • Writing test cases and test benches(Verilog) for design verification • Synthesis and LEC run for designs

Stackforce AI infers this person is a DFT specialist in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 6 mos