Atun Tripathy — Software Engineer

I am an experienced ASIC Physical Design Implementation engineer with nearly 11+ years in the semiconductor industry, specializing in CAD development for place-and-route (PnR) stages. Throughout my career, I have successfully completed over 10 tapeouts, working on cutting-edge technologies ranging from 2nm to 28nm nodes. My expertise spans the entire PnR flow, including floorplanning, power grid creation, placement, clock tree synthesis (CTS), routing, and timing closure. I have deep knowledge of standard cell profiling, library usage, and low-power design strategies, with extensive experience in multi-power domain partitions and Unified Power Format (UPF). I am adept at optimizing power, performance, area, and runtime (PPA) across diverse designs and have contributed to benchmarking and developing design methodologies for efficient PnR implementations. I have hands-on experience in physical verification, synthesis, static timing analysis (STA), and timing closure at the partition level. Additionally, I excel at design planning activities such as technology node selection, metal stack decisions, library and memory choice, and track/VT selection, ensuring robust and efficient designs. Beyond technical skills, I have successfully led small implementation teams, coordinating parallel efforts across multiple teams to drive design convergence and resolve critical design challenges. I enjoy finding flow optimizations and design recipes that accelerate tapeout readiness. Tools I work with: Fusion Compiler, ICC2/ICC, Innovus (PnR), DCT (Synthesis), PrimeTime (STA), RedHawk (IR), STAR-RC (Extraction), Calibre (PV), and extensive TCL scripting. I am passionate about delivering high-quality physical designs that balance power, performance, and area, and I am open to new opportunities where I can leverage my skills to drive successful tapeouts and team collaboration.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with extensive experience in ASIC design and PnR methodologies.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 11 mos