Jainil Shah — Product Engineer

🎓M.E. Microelectronics | BITS Pilani, Hyderabad Interested in RTL Design, Verification (SoC/Chip-Level), Physical Design, and Digital Implementation. Passionate about digital hardware and RTL design, with hands-on experience building and verifying logic in Verilog and SystemVerilog. I enjoy creating structured state machines, protocol-driven interfaces, and timing-aware datapaths, with a focus on clean, efficient design. 🛠Core Skills: ✓Digital Design: RTL coding, synchronous logic, FSM design, datapath structuring. ✓Verification Basics: SystemVerilog-based testbench creation, waveform debugging, simple assertion-based checks. ✓Timing & Optimization: Pipelining, Clock gating, Reset strategies, basic STA reasoning. ✓Protocols & Interfaces: AMBA-style handshakes and bus communication. ✓Tools Exposure: Cadence tools, Xilinx Vivado ✓Programming: Verilog, C, C++ 📌Hands-on Work: ✓Designed small to mid-scale RTL blocks (FIFOs, controllers, bridges, counters, datapaths). ✓Implemented and verified modules using the AMBA APB protocol, including interface logic and register-level operations. ✓Built an FSM-based control module for multi-step input handling and output sequencing (Verilog). ✓Simulated digital pipelines and validated behavior across corner scenarios. ✓Improved timing through clean design practices ard early optimization.

Stackforce AI infers this person is a Digital Design Engineer with expertise in RTL design and verification for semiconductor industries.

Location: Bengaluru, Karnataka, India

Experience: 4 mos