Nagarjuna Udutha

CEO

Hyderabad, Telangana, India15 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC Verification and UVM Test benches.
Proficient in automation using Perl and Python.
Experience with complex Ethernet protocols and coverage closure.

Stackforce AI infers this person is a highly skilled ASIC Verification Engineer with expertise in complex protocol verification.

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Skills

Core Skills

Asic VerificationSystemverilog

Other Skills

Interpersonal SkillsComputer ArchitectureCache CoherencyHigh Performance Computing (HPC)VerilogVHDLVLSIHardware DesignFPGAPost Silicon ValidationPerlTCLPythonSilicon ValidationHardware Architecture

About

Skilled in ASIC Verification with demonstrated history of developing System Verilog/ Universal Verification Methodology (UVM) Test benches from Scratch. Developed Testplans for Complex ASICs and closed Functional Coverage and Code Coverage. Excellent Triage and Debug skills. Adopted automation through Perl/Python for enhancing verification productivity. Learning about AI features of EDA tools for achieving Faster coverage closure as well as weeding out over-constraints. Protocols : Ethernet 802.3 10G/40G/50G MAC+PHY, USXGMII. AXI-Streaming, AXI4, AHB. Camera ISP. GFXIP L0$ and L2$, Cache Coherency.

Experience

15 yrs 2 mos

Total Experience

3 yrs

Average Tenure

4 yrs 5 mos

Current Experience

Amd

Senior Member Of Technical Staff

Dec 2021 – Present · 4 yrs 5 mos · India · Hybrid

Interpersonal SkillsComputer ArchitectureASIC VerificationSystemVerilog

Qualcomm

2 roles

Staff Engineer

Nov 2020 – Dec 2021 · 1 yr 1 mo

Interpersonal Skills

Lead Engineer, Sr

May 2018 – Nov 2020 · 2 yrs 6 mos

I am part of Camera ISP IP Design Verification Team.

Interpersonal Skills

Xilinx

Senior Design Engineer - I

Apr 2017 – May 2018 · 1 yr 1 mo · Hyderabad Area, India

I am involved in the Verification of Ethernet IPs (10G/25G/40G/50Gbps), AXI-4, AXI-4 lite, AXI-4 Streaming. Code Coverage and Functional Verification using Custom SVTB.

Interpersonal Skills

Vitesse semiconductor is now microsemi

2 roles

MTS-Verification

Promoted

Apr 2013 – Mar 2017 · 3 yrs 11 mos · Hyderabad Area, India

Development of Agents, Test Bench components and integration of Test Bench using SV/OVM/UVM based Methodologies. Handling complex Chip-level and IP-level Test Benches.
Development of Test plans and Verification Architecture for verifying Ethernet PHYs (1G/10G).
Functional Coverage and Code coverage of the same.
Protocols: SGMII, QSGMII, RGMII, XGMII, 10/100/1000BASE-T, 100/1000BASE-FX, 2.5G/5G/10GBASE-T, 10GBASE-X, 10GBASE-R, SPI, I2C, MDIO, IEEE-1588, MACsec. IEEE-802.3

Interpersonal Skills

Verification Engineer

Jul 2011 – Apr 2013 · 1 yr 9 mos · Hyderabad Area, India

Functional Verification of 1G PHY. Protocols SGMII, QSGMII, RGMII, 10/100/1000BASE-T and 100/1000BASE-Fx.
Development of Test cases based on SV/OVM Methodology. Development of Register Model using OVM-RGM.
Post-Si Validation of 10G PHY with OTN/FEC

Nvidia

Verification Intern

Jan 2011 – Jun 2011 · 5 mos · Bangalore

I was involved in Full-chip RTL Performance Verification of GPUs. It involved regression testing and debugging the failures. I gained a Top-level understanding of the GPU Architecture.