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Bhargav Hrishikesh

Software Engineer

Bengaluru, Karnataka, India8 yrs experience
Highly Stable

Key Highlights

  • Experienced in PDK and Layout Verification at Intel.
  • Developed test schematics for circuit functionality.
  • Strong foundation in VLSI and Embedded Systems.
Stackforce AI infers this person is a VLSI Engineer with expertise in PDK and circuit design.

Contact

hrishikesh.bhargav121@gmail.comLinkedIn

Skills

Core Skills

Pdk

Other Skills

Layout VerificationParasitic ExtractionCircuit DesignLayout DesignModeling and SimulationPhysical VerificationCVerilogMicrosoft OfficeElectronicsCommunication

Experience

8 yrs
Total Experience
8 yrs
Average Tenure
8 yrs
Current Experience

Intel corporation

PDK QA Engineer

May 2018 – Present · 8 yrs · Bengaluru

PDKLayout Verification

Intel corporation

Graduate Technical Intern

Jul 2016 – May 2017 · 10 mos · Bengaluru Area, India

  • My role as an intern in the Analog Circuit team involved building test schematics for developed designs to test functionality, obtain the best and worst case scenarios across corners and interact with senior designers to make any changes necessary.
PDK

Education

B. M. S. College of Engineering

Master of Technology — VLSI and Embedded System

Jan 2015 – Jan 2017

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