THANUJA J

Product Engineer

Bengaluru, Karnataka, India12 yrs 2 mos experience

Highly Stable

Key Highlights

Experienced in Physical Design and VLSI methodologies.
Strong background in semiconductor layout verification.
Proficient in Place & Route and Design Rule Checking.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and VLSI methodologies.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

Place & RouteDesign Rule Checking (DRC)Total SynthesisP&RSystem on a Chip (SoC)FloorplanningFloorplanning place nd routeDesignLow-power DesignScriptingPNRsynthesisSTALayout VerificationVlsi backend

Experience

12 yrs 2 mos

Total Experience

12 yrs 2 mos

Average Tenure

12 yrs 2 mos

Current Experience

– Present

Intel corporation

2 roles

Physical Design Engineer

Mar 2014 – Present · 12 yrs 2 mos · Greater Bengaluru Area

Place & RouteDesign Rule Checking (DRC)Physical DesignVLSI

Internship

– Present

Layout verification

Education

GIOE

Diploma of Education — Embedded systems

Aug 2010 – May 2013

BITS Pilani Work Integrated Learning Programmes

Bachelor of Technology - BTech

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