Anirudha Kulkarni

Software Engineer

Bengaluru, Karnataka, India31 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SoC Design and DFT methodologies.
  • Led successful projects in Set Top Box domain.
  • Extensive experience in RTL to GDS flow.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC and DFT methodologies.

Contact

Skills

Core Skills

Soc DesignDftSoc DftTest VerificationPattern Debug SupportIp Dft MethodologyTcl ScriptingFpga SynthesisAsic Conversion

Other Skills

SoCRTL designEmbedded SystemsASICStatic Timing AnalysisDebuggingTestingSemiconductorsPower SystemsVerificationDigital Signal ProcessingWireless NetworkingWireless Communications Systems

About

 Specialty : SoC Design, Design For Test  Active involvement in RTL to GDS flow and signoff in many tape outs  SoC and IP Design and verification  Execution and technical management of many projects  Domain knowledge : Scan Synthesis, STA, CTS  Cross domain knowledge : DVB, 3G, WCDMA, 802.11a, DSP, Digital Communication  EDA Tools Experience : Synopsys Tetramax, Design Compiler, and PrimeTime, Cadence NcSim  HDL : VHDL, Verilog  A little bit hands on with TCL and C Managed and executed projects as a SoC DFT lead for Set Top Box SoC Worked on many SoCs and their variants with successful execution. Some of the products that I worked on were best selling products in Set Top Box Domain Managed and executed IP Design and verification for 3GPP UE design, verification, FPGA synthesis, and FPGA to ASIC conversion

Experience

31 yrs 4 mos
Total Experience
4 yrs 6 mos
Average Tenure
10 yrs 8 mos
Current Experience

Intel corporation

Component Design Engineer

Sep 2015Present · 10 yrs 8 mos

Stmicroelectronics

5 roles

Senior Staff Engineer

Promoted

May 2012Aug 2015 · 3 yrs 3 mos

  • Full responsibility of SoC DFT
  • Manage technical activities of associated engineers
SoC DesignDFT

Senior Engineering Specialist

Promoted

May 2009Jan 2012 · 2 yrs 8 mos · Greater Noida

  • SoC DFT for Set Top Box products
  • Test architecture
  • Test mode TA
  • Test verification
  • Pattern generation
  • Silicon debug
SoC DFTTest Verification

Engineering Specialist

Jan 2006Jan 2009 · 3 yrs

  • SoC DFT Architecture, Design, and Execution
  • Pattern Debug Support
SoC DFTPattern Debug Support

Senior Design Engineer

Promoted

Jan 2004Jan 2006 · 2 yrs

  • SoC DFT Design and Execution
  • Pattern Debug Support
SoC DFTPattern Debug Support

Design Engineer

Jan 2002Jan 2004 · 2 yrs

  • IP DFT Methodology
  • TCL Scripting for DFT Methodology
IP DFT MethodologyTCL Scripting

Dcm technologies

Team Leader

Oct 1999May 2002 · 2 yrs 7 mos · Gurgaon, India

  • Worked on design, verificaion, FPGA synthesis, FPGA to ASIC conversion for 3GPP project of NEC Australia
  • Worked on 802.11a PHY development
FPGA SynthesisASIC Conversion

Cg-coreel logic systems

Design Engineer

Mar 1997Oct 1999 · 2 yrs 7 mos

  • Worked on CTI system integration. Designed and validated daughter boards of Subscriber Line Interface Circuits.

Db electronics

Customer Support Engineer

Jul 1993May 1996 · 2 yrs 10 mos

  • Customer Support for industrial power systems including solar power generators

Education

Birla Institute of Technology and Science, Pilani

ME — Microelectronics

Jan 1995Jan 1996

BE — Electronics

Jan 1988Jan 1992

Shivaji Science College

Higher Secondary School

Jan 1986Jan 1988

Manibai Gujrati Highschool

Jan 1981Jan 1986

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