G

Gopesh Singh

DevOps Engineer

New Delhi, Delhi, India2 yrs 2 mos experience

Key Highlights

  • MTech graduate with VLSI expertise.
  • Hands-on experience in SoC physical design.
  • Proficient in TCL scripting and design rule checking.
Stackforce AI infers this person is a VLSI design engineer with a focus on physical design and electronic engineering.

Contact

Skills

Core Skills

Physical DesignSoc Design

Other Skills

Design Rule Checking (DRC)Electronic EngineeringTransistorsECOHardware EngineeringUnified Power Format (UPF)RTL DesignField-Programmable Gate Arrays (FPGA)Layout Versus Schematic (LVS)TimingStatic Timing AnalysisElectrical EngineeringPower AnalysisLow-power DesignVerilog

About

• An MTech postgraduate with nearly 2 years of experience in the VLSI domain working for intel. • Designated as an SoC design engineer with experience in analog routing layout. • Have exposure to TCL scripting in fusion compiler. • Possess a basic understanding of PrimeTime. Core Competency: • Fusion Compiler, ICC2, IC Validator, PrimeTime, Unix & TCL. Personal Interests: • An all-around player, and hard worker with the ability to multitask and work across teams • Good Presentation Skills - Technical & Non-Technical Presentation Skills • Proficient in English, Hindi & Punjabi. • Hobbies: Writing songs, Instrumental music, playing cricket & volleyball. #phsyicaldesign #socdesign #electronicengineer #analogrouting #pnr #ppa #ptpx #rtlfp #rtl2gds #pinplacement #fusioncompiler #icc2 #ICCII #STA #vlsi #tcl #primetime

Experience

2 yrs 2 mos
Total Experience
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Average Tenure
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Current Experience

Department of telecommunications ( dot )

Assistant Divisional Engineer - Telecom

Aug 2025Present · 10 mos

Office of the controller general of patents, designs and trade marks (cgpdtm)

Examiner of Patents and Designs

Jan 2025Aug 2025 · 7 mos · On-site

Intel corporation

2 roles

SoC Physical Design Engineer

Jun 2022Mar 2023 · 9 mos

Design Rule Checking (DRC)Electronic EngineeringPhysical DesignSoC Design

Intern

Jun 2021Jun 2022 · 1 yr

Design Rule Checking (DRC)Electronic EngineeringPhysical DesignSoC Design

Tata communications

Network Engineer

May 2019Jul 2019 · 2 mos · Vishakhapatnam, Andhra Pradesh, India

Jio

Network Engineer

Jun 2018Jul 2018 · 1 mo · New Delhi, Delhi, India

Education

National Institute of Technology Delhi

Master of Technology - MTech — VLSI Design

Sep 2020May 2022

National Institute of Technology Delhi

Bachelor of Technology

Jan 2016Jan 2020

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