Vinay Kumar P P

Engineering Manager

Bengaluru, Karnataka, India26 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Proven leadership in engineering management at Intel.
  • Expertise in VLSI and ASIC design methodologies.
  • Strong background in static timing analysis and physical design.
Stackforce AI infers this person is a VLSI and ASIC design expert with strong engineering management skills.

Contact

LinkedIn

Skills

Core Skills

Engineering ManagementEngineering Leadership

Other Skills

Team ManagementStatic Timing AnalysisClock Tree SynthesisRTL verificationRTL designPhysical DesignFormal VerificationTCLPerl ScriptTiming ClosureVLSIASICSoCVerilogFunctional Verification

About

STA & Physical Design

Experience

26 yrs
Total Experience
6 yrs 6 mos
Average Tenure
17 yrs 8 mos
Current Experience

Intel corporation

2 roles

Engineering Manager

Promoted

Jan 2015 – Present · 11 yrs 5 mos

Team ManagementEngineering LeadershipEngineering ManagementStatic Timing AnalysisClock Tree SynthesisRTL verification+23

Graphics Hardware Engineer

Oct 2008 – Jan 2024 · 15 yrs 3 mos

Engineering ManagementEngineering Leadership

Qualcomm india pvt. ltd.

Lead Engineer, Sr

Jun 2008 – Sep 2008 · 3 mos

Engineering Leadership

Freescale india pvt ltd

Lead Engineer

Apr 2004 – May 2008 · 4 yrs 1 mo

Engineering Leadership

Motorola

Design Engineer

Jan 2000 – Jan 2004 · 4 yrs

Education

Vellore Institute of Technology

Bachelor Of Engineering — Electronics and communication

Jan 1994 – Jan 1997

Kendriya Vidyalaya

Higher Secondary School Education

Jan 1980 – Jan 1992

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