Nagaraja Ontk

Software Engineer

Bengaluru, Karnataka, India11 yrs 10 mos experience

Highly Stable

Key Highlights

Expert in Memory Layout Design across multiple technology nodes.
Hands-on experience with SRAM Physical Verification.
Proficient in Leaf Cells Layout Design and integration.

Stackforce AI infers this person is a Memory Layout Design Engineer with expertise in VLSI and ASIC technologies.

Contact

Skills

Core Skills

Memory Layout DesignPhysical VerificationLeaf Cells Layout Design

Other Skills

ASICVLSIEM/IRDFM checksSRAM CompilerLeaf cell layout designFINFetDouble PatterningSRAMAnalogAnalog Layout DesignStandard Cell Layout DesignWindowsIC LayoutLinux

About

Memory Layout Design Engineer Experienced in different technology nodes: Samsung >> 3lpe, 4lpe, 5lpe, 7lpe, 11lpp, 14lpp TSMC >> 3ff, 4ff, 7ff, 28nm, 90nm, 250nm. Handled complete project from scratch to top level. Hands on experience in Leaf Cells Layout Design(I/O, Rowdec, GBC, LBC) from scratch and top level integration. Physical Verification of SRAM. EM/IR, antenna, softcheck, DFM checks. Worked on compiler and custom Layout Design such as PDP, RF, SP, CPU etc. Standard Cells Layout design(6-tracks) in 28nm technology node

Experience

11 yrs 10 mos

Total Experience

4 yrs 5 mos

Average Tenure

4 yrs

Current Experience

Broadcom inc.

R&D Engineer IC Design 3

Jun 2022 – Present · 4 yrs · Bengaluru, Karnataka, India

ASICVLSIMemory Layout DesignPhysical VerificationEM/IRDFM checks

Qualcomm

2 roles

Engineer III at Qualcomm

Oct 2020 – Jun 2022 · 1 yr 8 mos

Engineer Il

Jun 2016 – Jun 2022 · 6 yrs

Memory Layout Design

Memory Layout Design

Alten calsoft labs

Design Engineer

Jun 2016 – Jun 2020 · 4 yrs · Bengaluru Area, India

Layout Design Engineer

Esilicon

Contractor

Mar 2016 – May 2016 · 2 mos · Da Nang, Vietnam

Worked on 14nm FF(Samsung) Technology
Completely worked on IO Block of SRAM
Leaf cell layout design of IO block for Compiler
Top level IO integration
Physical Verification(DRC/LVS), ERC, Ext, SoftCheck

Physical VerificationLeaf cell layout design

Si2chip technologies pvt. ltd.

Design Engineer

Jan 2015 – Jun 2022 · 7 yrs 5 mos · Bangalore

Leaf Cells Layout Design and Physical Verification of SRAM Compiler.
Layout design of SRAM 6T Bitcell and integration in Memory core array.
Layout design of Wordline decoder.
Layout design of Precharge & mux, Sense amplifier, Write driver and D-out of I/O Block.
Layout design of Pre-decoder's, Column select of Control Block.
Physical Verification.
Top Level Integration of SRAM Layout.

Leaf Cells Layout DesignPhysical VerificationSRAM Compiler

Rv-vlsi design center

Full Custom Layout Design trainee

Mar 2014 – Aug 2014 · 5 mos · Bengaluru Area, India

Leaf cells layout design of Compiler SRAM including top level routing in 28nm technology.
Designed layout of analog blocks.
Standard Cells layout design in 28nm and 90nm technology.
Physical verification(DRC/LVS) by using Calibre.

Leaf cells layout designPhysical verification