Haripriya Yada — CTO

• Constrained internal sub modules separately to reduce logic depth for better optimization at compile stage. • Cleaned floorplan base DRC by doing multiple floorplan iterations. • Implemented different experiments with dissolving RP’s, Routing guides on RP’s and Anchoring RPs in order to reduce shorts on RPD and congestion. • Manual placement of retimers using TCL script. • Applied DDR bounds to meet DDR specifications in order to meet DDR timing. • Improvement of CTS ID helps in reducing no of hold violations both @ block level and FCT level & improving power numbers. • Analyzed the track utilization with TCL script. • Created frame view of partition and instantiated in wrapper. • Clock_gating violations fixed by using use full skew method. • Routed nets manually in order to meet timing at ECO stage for critical paths. • Written multiple ECO’s to fix DRV, setup & hold violations .

Stackforce AI infers this person is a Physical Design Engineer with expertise in advanced semiconductor technologies.

Experience: 7 yrs