Sandeep J.

Software Engineer

Bengaluru, Karnataka, India13 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT Design and Physical Design.
Proficient in multiple EDA tools and methodologies.
Strong background in VLSI Design and Embedded Systems.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in DFT methodologies and EDA tools.

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Skills

Core Skills

Dft DesignPhysical DesignEmbedded ProgrammingVlsi DesignRtl Verification

Other Skills

VerilogVHDLUnixLinuxPerlShell ScriptingLayout and CharacterizationDRCLVSScan InsertionAutomatic Test Pattern Generation (ATPG)SimulationsASICCC++

About

Skill Set: DFT Design, Physical Design EDA Tools Experience:- • Mentor’s DFTAdvisor • Mentor’s Fastscan, Testkompress, Tessent • Synopsys Design Compiler • Synopsys TetraMax • Synopsys VCS, Verdi • Mentor’s Calibre DRC/LVS/XRC • Mentor's Modelsim • Cadence’s Virtuoso, NCSim,Encounter • Tanner’s L-Edit, T-Spice, S-Edit, W-Edit Specialties Scan Insertion, ATPG Pattern Generation and Verification

Experience

13 yrs 2 mos

Total Experience

2 yrs 10 mos

Average Tenure

7 yrs 3 mos

Current Experience

Amd

DFT Engineer (Client)

Aug 2019 – Oct 2021 · 2 yrs 2 mos

DFT DesignPhysical Design

Centaurs semiconductors private limited

Sr DFT Engineer

Mar 2019 – Present · 7 yrs 3 mos · Bangalore

DFT DesignPhysical Design

Qualcomm

DFT Engineer (Client)

Oct 2018 – Aug 2019 · 10 mos

DFT DesignPhysical Design

Amd

DFT Engineer (client)

Sep 2017 – Oct 2018 · 1 yr 1 mo · Bangalore

DFT DesignPhysical Design

Kenforce and imspired technologies pvt. ltd.

DFT Engineer

Aug 2017 – Feb 2019 · 1 yr 6 mos · Bangalore

DFT DesignPhysical Design

Itdp

Technical Trainer

Mar 2013 – Jul 2017 · 4 yrs 4 mos · Bhopal Area, India

Programming using verilog and VHDL
Embedded Programming
Programming of shell script(bash) and perl in Unix/Linux internal programming (gcc)
Formulate case studies and test patterns for assessing the group
Project work
Collaborative : CRISP
Lab(s): Analog and Digital Electronics Lab
HDL Lab (Prototype boards : Spartan 3, CoolRunner , Tools : Xilinx ISE )
VLSI (simulation Lab- tools used - AVR studio,Microwind, Modelsim)

VerilogVHDLUnixLinuxPerlShell Scripting+2

Freescale semiconductor

Post Graduate Intern

Mar 2012 – Dec 2012 · 9 mos · Noida Area, India

I have joined internship program at Freescale Semiconductor, NOIDA in TSO(TVG Soc) group. During internship tenure I worked in both Front-end and Back -end areas.
Layout and Characterization of Standard Cells (40 nm Technology)
Layout and Schematic of different cells using Virtuoso
DRC by CALIBRE
LVS by CALIBRE
RTL verification using NCsim
SDF generation by Encounter
TSMC18_ALLCELLS
Project Details:-Verifying RTL of TSMC18_ALLCELLS,Testcases ,Tasks & Testbench Generation,
Functional Simulation,Sequentional Simulation & Power Simulation(Static).
Project Detail :- Writing testbench for ROs,
Verifying the RTL of ROs,
Check different waveforms of ROs and find their Duty cycle,
SDF generation and Delay measurement.