Nov 2021 – Jul 2022 · 8 mos

• physical designing of IP's, Infrastructure tiles, Modem and/or DDR for the Qualcomm premium tier snapdragon platform (7/5/4 nm)
• Different design complexities included multiple clocks balancing requirements, sub-systems with 6 sub-blocks with 1 million instances each, ~2 million instance designs, 1.2 Ghz frequency , ~5K feedthroughs, 8 voltage domains, primary power switchable designs / power switches enabled , power muxes, analog + digital IP's , custom clock structure , congestion and timing critical designs etc.

Aug 2018 – Nov 2021 · 3 yrs 3 mos

May 2017 – Jun 2018 · 1 yr 1 mo · Noida Area, India

• Worked on all the aspects of Synthesis, Physical Design and Signoff including Floor Planning, Power Plan, Place and Route,
• Clock Planning and Clock Tree Synthesis, Parasitic Extraction, Timing Closure, Power / IR Drop (Static), Signal Integrity
• Analysis, Physical Verification (DRC, ERC, LVS) and DFM.
• Tools: Genus, Innovus/ Encounter, Spyglass Constraints checker, Tempus, Calibre, Voltus, StarRC

Dec 2013 – May 2017 · 3 yrs 5 mos · Noida Area, India

• Worked as a part of deployment team to provide technical support for users of Olympus/Nitro-SoC (Mentor Graphics complete digital implementation system for advanced-node ICs and SoCs). Providing custom scripts, design flows and detailed tool diagnostics for digital physical design at advanced nodes (28nm, 16nm, 10nm, 7nm).
• Specialties: Strong physical design, analysis and debug experience.
• Responsibilities included:
• Implementation (PnR) of multimillion gate SoC designs in cutting edge process technologies (28nm, 16nm, 10nm & 7nm) using Nitro-SoC.
• All aspects of Physical Design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY.
• Innovate on the flows to meet the QoR targets and ensure predictability using Nitro-SoC
• Exposure to the latest design rules, processes and innovations need to close PPA on the advance nodes.

Jul 2013 – Dec 2013 · 5 mos · Noida Area, India

• “Worked On AMBA & I2C Bus Design and Verification”, “FPGA Implementation” & “Physical Design & Verification”

Dec 2012 – Apr 2013 · 4 mos · Bangaluru

• Worked on 4 projects from schematic level to layout with Electronics Corporation of India Limited (Government of India Enterprise) under Computer Education Division titled
• >Physical Design & Analysis of Low Voltage Operational Amplifier
• >8-bit ADC
• >Design of Small Signal LNA
• >RISC based 32-bit general purpose microprocessor in Verilog