Aishwarya Kagalkar — Software Engineer
Passionate about semiconductor technology and enjoy working with the bits and bytes :-) I would love constantly endeavor to explore and develop something new out of my experience in RTL Design and knowledge of Front-end VLSI flows. Currently working as SoC Design Engineer at Intel. I am skilled with Verilog and System Verilog for RTL design. I have experience of working in RTL integration, RTL quality checks like Lint and CDC. I have good understanding of Design Constraints, Static Timing Analysis, Synthesis Flow. Have good knowledge of industry standard communication protocols like AMBA AXI, AHB, APB protocols. I am also skilled in Design Verification using System Verilog. Universal Verification Methodology(UVM).
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and VLSI technologies.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs
Skills
- Rtl Design
- System Verilog
Career Highlights
- Expertise in RTL Design and VLSI flows
- Proficient in Verilog and System Verilog
- Strong background in design verification and UVM
Work Experience
Intel Corporation
SoC Design Engineer (4 yrs)
Cadence Design Systems
Solutions Engineer II (3 mos)
Intern Solutions (8 mos)
Intel Corporation
Intern (1 yr)
Education
Master of Technology - MTech at Ramaiah Institute Of Technology
Bachelor of Engineering - BE at B V B College of Engg. & Technology, HUBLI
class 12 at Shri Dharmasthala Manjunatheshwar Pre university College dharwad
