Sep 2016 – Dec 2024 · 8 yrs 3 mos · Bangalore

• Lead a team, owned and delivered the LPDDR5/DDR5, High Speed Die-to-Die SerDes, MemPHY (GMI/xGMI/PCIe), PLLs and TestChips for leading technology nodes for all AMD products
• Built a new verification team for SerDes from scratch and delivered firstpass flawless Silicon
• Expertise in driving and leading the IP Verification, effort estimation and scoping of Verification
• Responsible for overall sign-off for pre-silicon verification
• Technical expertise includes Team building, Leading a team, Functional Verification, Firmware Verification, Gate Simulation (GLS), Low Power / Power aware Verification, Analog Mixed Signal Verification (AMS), Formal Verification, RNM DV (Real Number Model), TestBench Architecture and RISC-V.

Jul 2012 – Jun 2016 · 3 yrs 11 mos

• Worked on Intel's Mobile/tablet SoC, Quark IoT, Intel’s next generation client Microprocessors, FuseHIP BMod
• Owned and was responsible for PowerManagement and Reset flow integration verification for BDC owned IPs (Connectivity, Security and eSPI IPs) for Intel’s next generation Client MicroProcessor.
• Owned, enabled and performed the Formal Verification, Power Aware Verification and Power-Estimation for Intel’s two IoT products including Quark D2000;
• Worked on validation technical readiness of Low Power Imaging and Image Unit for Intel’s next generation wearable product; lead the validation tasks for these areas and prepared/proposed the validation plan including environment and test scenarios for this.
• Worked on the pre-si verification of Global Flows. This includes the verification of SoC Fuse Unit, Boot/Reset Flow, System Controller Unit, and LSP validation for Intel’s Merrifield and Moorefield platform SoC for Mobile and Tablet products;
• Lead and delivered the FuseHip BMODs for approximate 7 projects Intel-wide. This also included the design and verification.
• Worked on enabling the Formal Verification for SoC project and PoCed the JasperGold based formal application FPV, connectivity analysis, X-prop, SEC and Low Power Validation.

Jul 2006 – Jun 2012 · 5 yrs 11 mos

• Worked on Multiple generations of Intel Server processor design verification including Intel Xeon 7400 series (6 cores) and Intel Xeon E7 server (10 Core) as Individual Contributor.
• Owned the Global feature validation of Power-Up/Reset/MP-Init/Clocks, Virtual Fuses, and Initialization Firmware; Also worked on Intel Architecture Validation (IAV), Feature Architectural Validation (FAV).
• Tasks involved continuous integration, test plan development, Full-chip infrastructure / Environment development and support,
• Test stimulus writing, Test plan writing, Validation and debug. Involved in full life cycle of the project (Pre-silicon, Component Debug and Post-silicon debug and support)
• Misc: Development of End of test Memory Coherency Checker, Cache Preloader

Apr 2004 – Jul 2006 · 2 yrs 3 mos

• Worked on Intel’s proprietary validation tools development (Emulation system and Simulator); this included adding few features
• in System Verilog Front End development for Intel’s Internal Simulator and enhancement of technology mapping tool for Intel’s
• internal Emulation System.

Jan 2003 – Jan 2004 · 1 yr · Bussiness Incubator, IIT Bombay, Mumbai

• Was involved in design and development of FPGA based Hardware Accelerator System in PowaiLabs. This included development and integration of a set of SW tools required for HW Accelerator. These tools includes debug hooks insertion in a design, VHDL coding, simulation, synthesis and design verification; Generating test cases to test the VHDL design and tool functionality; Developing
• test benches and functional models. A Generic synthesizable test bench design and development for FPGA based system.

Jan 2000 – Jan 2003 · 3 yrs

• Research Assistant at Microelectronics Lab (MCL) at IIT Bombay.

Jan 1998 – Jan 2000 · 2 yrs · Mumbai

• Total 2 years of experience in extensive application software development (Versatile Depository & Accounting System for CDSIL (CDSL), Bombay Stock Exchange, Mumbai and A Centralized Core Banking Solution). This involved software development in various stages of software life cycle such as requirements study, analysis, design, development, and implementation.