Amruth Kumar — Software Engineer

Physical Design Engineer with 6 years of end-to-end experience implementing RTL to GDSII flows for high-performance ASICs across Intel 18A to TSMC 22nm nodes. Proven expertise in floorplanning, power/clock planning, placement, CTS, routing, timing closure, extraction, and MCMM signoff (STA, DRC/LVS, EM/IR, Crosstalk). Delivered macro-heavy blocks up to 3.5M instances, meeting aggressive frequency and power goals with optimized PPA. Skilled in ICC2, Innovus, Genus, PrimeTime, Tempus, StarRC,Redhawk, and Voltus. Automated PD workflows using TCL and Perl, reducing manual effort time by 30–40%. Strong focus on timing optimization, clock gating, and low-power methodologies. Collaborated with cross-site global teams ensuring seamless execution, and mentored junior engineers to drive quality and efficiency. Passionate about innovation, collaboration, and continuous improvement in silicon design excellence.

Stackforce AI infers this person is a Physical Design Engineer specializing in ASIC design and low-power methodologies.

Location: Andhra Pradesh, India

Experience: 7 yrs 1 mo