Arjun S

Software Engineer

Bengaluru, Karnataka, India14 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in ASIC physical design and verification.
Led multiple full chip ownerships in advanced technology nodes.
Proficient in SoC floor planning and high-speed memory interfaces.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in ASIC and VLSI technologies.

Contact

Skills

Core Skills

SocFloorplanningHigh Speed ClockingPower StrategiesAsicVlsiPhysical DesignPhysical Verification

Other Skills

HBM2HBM3Full Chip SOC FloorplanVerilogCadence VirtuosoVHDLEmbedded SystemsXilinx ISEDRCPerlRTL designFunctional VerificationSystemVerilogModelSimTCL

About

Physical Design Implementation of ASIC's which includes Synthesis, floor planning, power planning, place and route, parasitic extraction, signal integrity analysis and repair, ECO, STA and Closure. Working on Full Chip and Block level Physical Design Verification(DNE). DRC/LVS/DFM/ESD/Latch up’s checks to ensure that Layout meets foundry requirements and design constraints.

Experience

14 yrs 7 mos

Total Experience

3 yrs

Average Tenure

2 yrs 4 mos

Current Experience

Alphawave semi

Senior Staff Engineer

Feb 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · Remote

Responsible for (High Bandwidth memory Interface Phy), High Speed Clocking strategies in IPs, Power & IR Strategies, HBM2 & HBM2e, HBM3, LPDDR4x5, UCIe implementation - TSMC, GF and Samsung
Architecting Interposer for a testchip on Chip-on-Wafer-on-Substrate (CoWos) technology (2.5D packaging)
Working on SoC floorplan, power plan, Bump plan etc as per JDEC/IEEE1500 Specification

SoCFloorplanning

Qualcomm

Staff Engineer

Jun 2016 – Jan 2024 · 7 yrs 7 mos · Greater Bengaluru Area

Physical Design Engineer, Working on cutting edge technology on DDR phy block and IPPD blocks
Working on Full Chip/Block Level Physical Design Implementation and Physical Verification.
Hands on experience in Full Chip SOC floorplan, RDL routing, Bump Assignment and Block level Full PD flows.
Worked on latest test chip and Production chip with latest technology node of 3ff(TSMC) and 3lpe(SEC)
Independently handled as many as 25 TO as full Chip owner
Physical Design Implementation of ASIC's which includes Floor planning, power planning, place and route, parasitic extraction, signal integrity analysis and repair, ECO, STA and Closure.
Physical Design Verification (DNE). DRC/LVS/DFM/ESD/EMIR, DFM, Signal-EM/Latch up’s checks to ensure that Layout meets foundry requirements and design constraints.

ASICVLSI

Conexant

Hardware Design Lead Engineer

Feb 2015 – Apr 2016 · 1 yr 2 mos · Greater Hyderabad Area

Working on Full Chip Physical design/Verification and Block level Physical Design Implementation
Physical Design Implementation of ASIC's which includes Floor planning, power planning, place and route, parasitic extraction, signal integrity analysis and repair, ECO, STA and Closure.
Physical Design Verification (DNE). DRC/LVS/DFM/ESD/EMIR, DFM, Signal-EM/Latch up’s checks to ensure that Layout meets foundry requirements and design constraints.
Tapeout/QA/Characterization activities for projects on different foundry’s, Standard cells, IO’s, Memories.

Lsi corporation

ASIC Design Engineer

May 2012 – Sep 2014 · 2 yrs 4 mos · Bengaluru, Karnataka, India

Worked on Full Chip Physical Verification and Block level Physical Design Implementation
Been a part of more than 15 Tapeouts, in which 7 Full chips handled independently on PV
Worked on mostly on 40nm, 28nm and started on 16FF
Having sound knowledge in DRC/LVS/DFM/ESD/Latch up’s checks to ensure that Layout meets foundry requirements and design constraints
Good knowledge in all aspects of IC design including floor planning, power planning, place and route, parasitic extraction, signal integrity analysis and repair, ECO.
Physical verification support for block designs (IP) and develops infrastructures to automate the physical verification.
Tools exposure ICC, Calibre, Rehawk, Cadences Virtuosu, Perl/Tcl.
Worked on Full chip/Block analog routing for DDR, PLL, Crystal Oscillator’s, SERDES etc.
Review’s for IP’s like DDR, PLL Oscillator’s & IO etc from Placements to signoff
Participates in architecture discussion and provide suggestion.
Troubleshooting and debugging problems and scripting using Calibre Runset & Scripting

Wipro technologies

Project Engg

Mar 2011 – May 2012 · 1 yr 2 mos · Bengaluru, Karnataka, India

VLSI Engg
Analog & Mixed Layout design and PD flow in VLSI domain. Floorplan & placement Designing Layout form schematics created by Design Engineers in 22nm technologies.DRC/LVS/DFM , GDS and netlist checks to ensure that Layout meets foundry requirements and design constraints.
Physical verification support for block designs(IP) and develop infrastructures to automate the physical verification.