AVIJIT NASKAR

Software Engineer

Bengaluru, Karnataka, India27 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 23 years of experience in SOC and IP verification.
Led teams of over 20 engineers in complex projects.
Expertise in DDR sub-system and ARM based NOC interconnect.

Stackforce AI infers this person is a Semiconductor and Networking expert with extensive experience in SOC design and verification.

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Skills

Core Skills

VerificationSystem DesignSoc DevelopmentSimulationMemory Controller DesignRtl DesignBus Architecture DesignTiming Analysis

Other Skills

DDR sub-system verificationNOC interconnectSystem coherence verificationModem sub-system verificationSOC backbone developmentFPGA prototype validationAutomotive Safety verificationCNA chip verificationFunctional/performance simulationSystem Verilog-VMM methodologyDDR-I/II Memory Controller developmentMicro-architecture developmentOn-chip bus architecture designSynthesisDDR memory controller development

About

Specialities: Next gen DDR sub-system, ARM based NOC interconnect, and System coherency * Seasoned Verification Leader with 23+ years experience in the complex SOC, Sub-system, IP verification for mobile and networking chip sets. Including 5 years of IP & Subs-system design and work exposure in safety verification. * Built new teams and managing more than 20+ engineers. * Managed multiple projects simultaneously – Pre SI verification and Post SI validation. * RTL design - DDR sub-system and Bus bridges * Process/productivity improvement for Pre SI DV. Certified internal auditor.

Experience

27 yrs 4 mos

Total Experience

4 yrs 6 mos

Average Tenure

9 yrs 11 mos

Current Experience

Qualcomm

2 roles

Principal Engineer/Manager

Promoted

Dec 2023 – Present · 2 yrs 6 mos

Sr. Staff/Mgr.

Jun 2016 – Nov 2023 · 7 yrs 5 mos

Leading next gen DDR sub-system, NOC interconnect and System coherence verification, worked on Modem sub-system verification.

DDR sub-system verificationNOC interconnectSystem coherence verificationModem sub-system verificationVerificationSystem Design

Nvidia

Senior ASIC Lead

Apr 2012 – Jun 2016 · 4 yrs 2 mos · Banagalore

Worked on SOC backbone development for nVidia Tegra mobile plateform.
Worked as a design & verif lead of a team of 10 peoples.
Primary responsibility is to drive SOC backbone development : Spec to Good quality netlist deliverable to PD, FPGA prototype validation and post SI validation.
Worked on Automotive Safety (ISO26262) verification.

SOC backbone developmentFPGA prototype validationAutomotive Safety verificationSOC DevelopmentVerification

Emulex

Principal Engineer

May 2006 – Mar 2012 · 5 yrs 10 mos · Bangalore

Worked as lead for verifying the multiple CNA chips (EMULEX : XE-210).
Responsible for the functional/performance simulation for various storage protocols, chip's processor complexes, bus & bridges.
Significantly contributed for verification sign-off with verifying chip's complex error recovery - Ethernet link bounce / recovery in mixed protocol mode, PCIe Functional Level Reset (FLR) recovery.
Successfully integrated System Verilog-VMM methodology in Emulex’s verification flow.
Actively worked in Emulex Process Team and guided in Emulex, Bangalore ISO certification for Engineering Development.

CNA chip verificationFunctional/performance simulationSystem Verilog-VMM methodologyVerificationSimulation

Aarohi communications

Staff Engineer

Jun 2004 – Apr 2006 · 1 yr 10 mos · Bangalore

Responsible for DDR-I/II Memory Controller (MC) Sub-system and PHY development.
Successfully made the DDR interface to work at target frequncy on Silicon.
Micro-architecture development, RTL design, verification to chip bring-up for storage controller chip.
Developed innovative Arbitration scheme for memory bandwidth curving among various on-chip agents.

DDR-I/II Memory Controller developmentMicro-architecture developmentRTL designMemory Controller DesignRTL Design

Texas instruments

Senior Design Engineer from Wipro

May 2002 – May 2004 · 2 yrs

Responsible for designing various on-chip bus architecture and bridges ( AMBA AHB and OCP).
These bridges were used for making Legacy IPs compatible to industry standard on-chip bus protocols.
Micro-architecture developement to Synthesis.
Responsible for timing analysis (STA) on post-layout netlist for Processor Complexes and peripheral.

On-chip bus architecture designTiming analysisSynthesisBus Architecture DesignTiming Analysis

Wipro technologies

Senior Designer/IP Lead

Sep 1998 – Apr 2002 · 3 yrs 7 mos

Responsible for DDR memory controller, PCI arbiter and lite PCI slave development.
Developed AMBA AHB verifcation IP and succesfully integrated in different groups' project.
Worked from PRD to time closure, also drove the verification activities.
DDR interface characterization and defined routing and trace guideline for system level design.

DDR memory controller developmentAMBA AHB verification IPVerification activitiesMemory Controller DesignVerification