chandrasekhar chippada — Product Engineer
Worked on SOC partitions, range of 0.5M - 5.5M Instances. Worked on PNR and ECO stage with Timing and Physical Verification Signoff. Worked on FULLCHIP FM checks. Tools known : ICC 2, PRIME TIME, Formality, Innovus, Tempus. Technology Node : 3nm, 4nm, 6 nm & 7 nm. Also having the 1yr 5 months experience in the Research and Development field as an Intern. Leading Role in the Project of CHANDRAYAAN 2(ISRO) competition.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expertise in Physical Design and Static Timing Analysis.
- Led initiatives in high-profile projects like CHANDRAYAAN 2.
- Proficient in advanced semiconductor technologies.
Work Experience
Broadcom
R&D IC Design Engineer (PD) (2 yrs)
MediaTek
Senior Engineer (2 yrs 5 mos)
SeviTech Systems Pvt. Ltd.
Senior Physical Design Engineer (6 mos)
Soctronics
Physical Design Engineer (2 yrs 7 mos)
AMD VEDA IIT
Graduate Engineer Trainee (6 mos)
Education
Master's degree at BITS Pilani Work Integrated Learning Programmes
Bachelor of Technology - BTech at gayatri vidya parishad college of engineering(autonomous)
Diplamo at G M R I T, Rajam
1st class - 10th class at sri vidhyaniketan high school