D

Darshana B.

Software Engineer

Bengaluru, Karnataka, India7 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expert in VLSI and ASIC design methodologies.
  • Proficient in DRC, LVS, and Static Timing Analysis.
  • Strong background in low-power design techniques.
Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC development.

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Skills

Core Skills

Very-large-scale Integration (vlsi)Application-specific Integrated Circuits (asic)

Other Skills

DRC and LVSAntenna checksERCRoot Cause AnalysisLinuxPNRStatic Timing AnalysisTCLClock Tree SynthesisOCVFloorplanningLayout Versus Schematic (LVS)Low-power DesignDesign Rule Checking (DRC)Synopsys IC Compiler

About

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Experience

7 yrs 1 mo
Total Experience
7 yrs 1 mo
Average Tenure
7 yrs 1 mo
Current Experience

Intel corporation

3 roles

GPU Physical Design Engineer (Clocking)

Apr 2024Present · 2 yrs 1 mo

DRC and LVSAntenna checksERCApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)Root Cause Analysis+18

SoC Design Engineer

Nov 2021May 2024 · 2 yrs 6 mos

Layout Verification Engineer

Apr 2019Nov 2021 · 2 yrs 7 mos

Education

Dibrugarh University, Dibrugarh

Bachelor of Technology (B.Tech.) — Electronics and Communication Engineering

Jan 2013Jan 2017

Maria's Public School, Guwahati

Jan 1998Jan 2013

Stackforce found 100+ more professionals with Very-large-scale Integration (vlsi) & Application-specific Integrated Circuits (asic)

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