Deepika Ahlawat

Founder

India12 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led development of PrimeTime, a leading timing analysis tool.
  • Mentored engineers across VLSI, FPGA, and ML domains.
  • Expert in US job search strategies for engineers.
Stackforce AI infers this person is a leader in EDA and semiconductor industries with expertise in VLSI and software development.

Contact

Skills

Core Skills

ManagementStatic Timing Analysis

Other Skills

C++Object-Oriented Programming (OOP)SystemVerilogTestingShell ScriptingCircuit DesignApplication-Specific Integrated Circuits (ASIC)VHDLLinuxPerlEmbedded CUnixMatlabSimulinkPython

About

Engineering leader with experience across Xilinx, MathWorks, Intel, and Synopsys, working in VLSI, EDA, ML/AI, and large-scale software development. Currently managing a team driving key features in PrimeTime, the industry’s most widely used timing analysis tool. Over the years, I’ve reviewed hundreds of resumes, interviewed dozens of engineers, and mentored talent across FPGA, ASIC, RTL, and ML domains. One pattern stands out: Strong engineers often struggle with career navigation especially when aiming for the US market. I share practical insights on: US job search strategy for engineers - What actually gets attention in a 3-second resume scan - How semiconductor/EDA hiring really works - Career growth for VLSI, FPGA, ASIC and software engineers - Leadership, team dynamics, and breaking into top tech roles My goal is simple: help engineers make smarter career moves with clear, experience-backed guidance. If you’re exploring US opportunities, transitioning roles, or growing in semiconductor/EDA, my content is built for you.

Experience

12 yrs 1 mo
Total Experience
3 yrs
Average Tenure
6 yrs 4 mos
Current Experience

Aim resume

Founder & CEO

Mar 2026Present · 2 mos

Synopsys inc

Research And Development Manager

Feb 2022Mar 2026 · 4 yrs 1 mo · Bengaluru, Karnataka, India

  • Lead an 8-member team delivering core features for PrimeTime, the industry’s most widely used static timing analysis tool.
  • Drive end-to-end development across design, implementation, optimization, and release workflows.
  • Mentor engineers in timing, C++, performance tuning, and large-scale debugging.
  • Review resumes, interview engineering candidates, and support hiring decisions.
  • Collaborate with cross-functional teams across EDA, synthesis, and verification.
ManagementStatic Timing Analysis

Intel corporation

EDA Software Engineer

Sep 2021Jan 2022 · 4 mos · Bangalore Urban, Karnataka, India

  • Contributed to internal tooling and flow development for semiconductor design.
  • Gained exposure to cross-team silicon development processes and validation methods.

Self-employed

Career Mentor (Volunteer / Community Support)

Jan 2020Present · 6 yrs 4 mos

  • Support engineers through resume review, job search strategy, and career positioning
  • Share guidance on US hiring patterns, ATS rules, and semiconductor/EDA interview expectations.
  • Provide insights on industry transitions (VLSI ↔ software ↔ ML).

Mathworks

Software Engineer II

Apr 2019Jun 2021 · 2 yrs 2 mos · India

  • Worked across Machine Learning/Deep Learning workflows.
  • Built scalable, high-performance MATLAB tooling and user-facing features.
  • Collaborated with global teams improving simulation and modeling systems.

Xilinx

Software Engineer II

Feb 2015Jan 2019 · 3 yrs 11 mos · Hydrabad

  • Developed arithmetic and linear algebra primitives for Xilinx Model Composer tool in Matlab using C++.
  • Created regression tests and unit tests for verification.
  • Maintained code sanity for good functional and code coverage.
  • Debugging the code using multiple debugger softwares was also handled.
  • Developed requirements specifications, user documentation, and architectural systems research.

Xinoe systems

Technical Trainer

Jan 2014Feb 2015 · 1 yr 1 mo · Gurugram, Haryana, India

  • Provided hands on trainings in Verilog, System-Verilog and UVM framework.
  • Conducted FPGA workshops in various colleges and universities.
  • Conducted Verilog trainings for DRDO
  • Created the content and course modules for the VLSI trainings.

Education

ITM University

Master of Technology (M.Tech.) — VLSI Design

Jan 2012Jan 2014

Maharshi Dayanand University

Bachelor of Technology (B.Tech.) — Electronics and Communications

Jan 2008Jan 2012

Central Board of Secondary Education

10+2

Jan 2008Present

Central Board of Secondary Education

10th

Jan 2006Present

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