Dheeraj Shetty

Software Engineer

Bengaluru, Karnataka, India13 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in Analog and VLSI design.
Led critical projects in high-speed mixed-signal design.
Strong academic background with top CGPA.

Stackforce AI infers this person is a highly skilled Analog Engineer in the semiconductor industry.

Contact

Skills

Core Skills

Circuit DesignVlsi

Other Skills

RX clocking pathPCIE G5 applicationsTX clocking optimizationtrack-hold generationsignal shaping driverclock jitter optimizationDFE designhigh-speed slicerdelay locked loopsduty cycle correctorCTLEverilog-A modelingConstant Gm designhigh-speed comparatorsMatlab/Simulink modeling

About

Passionate Analog Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Circuit design, Reliability validation , Matlab system modeling and Verilog. Strong engineering professional with a Master of Technology (M.Tech.) focused in VLSI Design from National Institute of Technology Karnataka.

Experience

13 yrs 8 mos

Total Experience

5 yrs 4 mos

Average Tenure

2 yrs 11 mos

Current Experience

Marvell technology

Principal Engineer

Jul 2023 – Present · 2 yrs 11 mos · Bengaluru, Karnataka, India · Hybrid

1. Leading the RX clocking path post PLL for automotive PHYs
2.Responsible for RX data path timing for PCIE G5 applications.

RX clocking pathPCIE G5 applicationsCircuit designVLSI

Intel corporation

3 roles

Senior Analog Design Engineer

Apr 2020 – Jun 2023 · 3 yrs 2 mos

Ethernet PHY
1. Explored optimizations for TX clocking for 224G serdes.
2. Owned track-hold generation and signal shaping driver plus dividers for RX clocking for 112G serdes.
3. Explored optimizations for clock jitter, IQC for PCIE G5+ clock routing.

TX clocking optimizationtrack-hold generationsignal shaping driverclock jitter optimizationCircuit designVLSI

Analog Design Engineer

Promoted

Apr 2017 – Mar 2020 · 2 yrs 11 mos

Working on High-Speed Mixed-Signal PHY Design
1. Owned design and post silicon characterization of G4 DFE and Squelch for PCIE.
2. Owned design of DFE and high speed slicer for MIPI protocol (Gen 2+) and post silicon
characterizing/ debug for multiple tape outs at lower technology nodes.
3. Have worked on delay locked loops, duty cycle corrector and CTLE for past projects.
Involved with verilog-A modeling for the control loops to bridge the gap in mixed signal validations.
4. Designed high PSRR and high performance LDO with both pass device variants.
5. Working closely with RTL/verification and layout team to ensure the quality and validation coverage. Also involves collaboration with Junior designers to help them root-cause the issues and guide them to close designs faster.

DFE designhigh-speed slicerdelay locked loopsduty cycle correctorCTLEverilog-A modeling+2

Component Design Engineer

Jul 2014 – Mar 2017 · 2 yrs 8 mos

Power Management and Modeling
1. Designed precision Constant Gm, V/R current biases along with voltage reference for analog cores.
2. Also worked on design of high speed auto-zero comparators employed in analog LDO's for calibration and Flash ADC for digital LDO's.
3. Matlab/ Simulink system modeling for digital LDO's with compensation and voltage, current mode of DC-DC converters.
4. Behavioral modeling of analog sub-blocks for LCVR and Switched Cap Voltage Regulators.

Constant Gm designhigh-speed comparatorsMatlab/Simulink modelingbehavioral modelingCircuit designVLSI