Dr Parag Bhatnagar

CTO

Bengaluru, Karnataka, India27 yrs experience

Highly Stable

Key Highlights

Led VLSI division growth to 130+ engineers.
Expert in Static Timing Analysis and Physical Design.
Strong background in Business Development in Semiconductors.

Stackforce AI infers this person is a Semiconductor Engineering Leader with extensive experience in VLSI and Physical Design.

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Skills

Core Skills

Physical DesignStatic Timing AnalysisBusiness Development

Other Skills

Low-power DesignLogic SynthesisMixed SignalRTL designTiming ClosureDebuggingSignal IntegritySemiconductorsEDAASICVerilogSoCPeople managementEngineering team-buildingRTL Design

Experience

27 yrs

Total Experience

3 yrs

Average Tenure

2 yrs 7 mos

Current Experience

Accenture

Silicon Engineering Director

Nov 2023 – Present · 2 yrs 7 mos · Bengaluru, Karnataka, India · On-site

Static Timing AnalysisPhysical DesignLow-power DesignLogic SynthesisMixed SignalRTL design+9

Qualcomm

SoC Program Manager

May 2023 – Nov 2023 · 6 mos

Intel corporation

Sr Engineering Manager

Sep 2018 – May 2023 · 4 yrs 8 mos · Bangalore

Insilico

Director of Engineering

Jan 2016 – Sep 2018 · 2 yrs 8 mos · Bangalore

Heading the vertical for VLSI division with a team of 130+ high performing engineers, working in latest technologies (14nm, 20nm and 45nm)
Responsibilities Includes:
Grown the vertical from scratch to 130+ in a year time frame.
Doing people management for the team i.e 1:1, skip level meetings, retention discussion etc.
Managing the recruitment team for VLSI vertical.
Managing all the escalations and deliverable from the clients.
Monitoring and tacking all the ODC/Turnkey projects
Business Development
Proliferating new Technologies and Solutions.

Mirafra technologies

Director Engineering - Physical Design

Dec 2014 – Dec 2015 · 1 yr · Bengaluru Area, India

Heading the Design Services Group with a team of 100+ high performing engineers, working in latest technology (14nm, 20nm, 45nm & 65nm) .
Responsibilities:
Business Development and Pre-sales support.
Engineering team-building.
Enhancing customer relationship and Delivery manager.
Proliferating new Technologies and Solutions (RTL-to-GDS)
Experience on operating style of a semiconductor Product Company, EDA and Design Service Company.

Cadence design systems

2 roles

Staff Product Engineer

Sep 2012 – Dec 2014 · 2 yrs 3 mos · Noida Area, India

Worked as a Staff Product Engineer for the logical & physical synthesis group.

Staff Application Engineer

Aug 2007 – Sep 2012 · 5 yrs 1 mo · Noida Area, India

Technical manager for Cadence Global Customer support team which are responsible for supporting India, Asia pacific, Europe and North America customer in EDI (P&R tool) /ETS (Timing tool).

Nxp semiconductors

Architect

Aug 2004 – Aug 2007 · 3 yrs · Bengaluru Area, India

Doing the Architect role for Block Implementation. Ownership of Physical Synthesis, Routing & Optimization, Extraction, STA, Crosstalk, IR Drop for Block Level.
Worked very close with Philips business units to develop there methodology along with the design.