Ganesh Machavarapu — Co-Founder

• 9+ years of experience in physical design (RTL to GDS) and Taped In multiple projects and also developed multiple automation flows/Automation tools in back end design. • Good in fixing toughest setup/hold problems even after automated fixing capabilities of EDA tools are exhausted. • Experience of going through multiple testchips/production tapeouts at latest nm • Experience of analyzing/resolving issues based on silicon feedback. • Hands on experience and in depth knowledge of full chip and block level ASIC design flow from synthesis to GDSII, involving deep submicron effects related to crosstalk/SI/glitch, metal fill, OCV/AOCV, process/voltage/temperature corners and power • Expert in identifying automation opportunities, and using various scripting languages (tcl, Python, tK,PERL,csh ad java frame work) on the fly to streamline/simplify repetitive tasks involving analysis/fixing violations and generate/parse/summarize useful reports and developed an automation to name called Streamliner in IINTEL. • Enjoys tough challenges, new learning opportunities and solving difficult problems • Experienced at leading and collaborating with different teams across different geographies Specialties: • Tools: FC Compiler,IC compiler, PrimeTime SI, StarRC, Design Compiler, Formality, Redhawk , Innovus and tempus • Languages/Scripts: Tcl, Python, Perl, awk, sed, C shell/Make, Java, C++, Verilog, Tk I have started a NGO called "SAAHASAM". from which I want to give better education for village children s. We are working on rural educational development.

Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on automation and physical design.

Location: Karnataka, India

Experience: 16 yrs 9 mos

Career Highlights

9+ years of experience in physical design.
Expert in automation tools and scripting languages.
Founder of NGO focused on rural education.

Work Experience

Qualcomm

Staff Physical Design Engineer (1 yr 10 mos)

Physical Design Engineer (3 yrs 10 mos)

Intel Corporation

System-on-Chip Design Engineer (3 yrs 9 mos)

Sahasam trust

Founder (10 yrs 1 mo)

Consultant at INTEL

Physical Design Engineer (1 yr)

Consultant at AmedRF

Physical Design Engineer (1 mo)

Consultant at Semtech

Physical Design Engineer (1 mo)

Sankalp Semiconductor Pvt Ltd

Physical Design Engineer (1 yr 6 mos)

Intel Corporation

Internship (8 mos)

VIT University

Graduate Student (1 yr 11 mos)

Avanthi Inistitute of Engineering and technology

Undergraduate Student (3 yrs 11 mos)

Education

Master of Technology (M.Tech.) at Vellore Institute of Technology

Bachelor of Technology (B.Tech.) at avanthi institute of engineering and technoogy

intermediate at Narayana Junior college,visakhapatnam

at Z.P.H School chanduluru

Ganesh Machavarapu

Co-Founder

Karnataka, India16 yrs 9 mos experience

Highly Stable

Key Highlights

9+ years of experience in physical design.
Expert in automation tools and scripting languages.
Founder of NGO focused on rural education.

Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on automation and physical design.

Contact

ganeshmachavarapu@gmail.com LinkedIn

Skills

Other Skills

VLSISoCVerilogPerlStatic Timing AnalysisCTCLCadence VirtuosoASICRTL DesignIntegrated Circuit DesignPhysical DesignUPFlow power techniquescc-opt

About

Experience

16 yrs 9 mos

Total Experience

3 yrs 8 mos

Average Tenure

1 yr 10 mos

Current Experience

Qualcomm

2 roles

Staff Physical Design Engineer

Promoted

Jul 2024 – Present · 1 yr 10 mos · India · On-site

Physical Design Engineer

Dec 2016 – Oct 2020 · 3 yrs 10 mos · Bangalore

I am working as a physical design engineer ....

Intel corporation

System-on-Chip Design Engineer

Oct 2020 – Jul 2024 · 3 yrs 9 mos · Bengaluru, Karnataka, India

After 6Years... Back to Intel... Same day where I have started my career as Intern again on same day I have joined back again Intel... #BackToHome

Sahasam trust

Founder

Apr 2016 – Present · 10 yrs 1 mo · Vizianagaram Area, India

Yes..., finally I have initiated my first step towards my goal....
Recently I had a great moment in this #Ugadhi vacation ...I want to share that moment with you all.
Really I had a wonderful,memorable and precious days in my life during this period. I met many people like parents,teachers and children's in remote villages, I spent so much time with them ,have learnt many things and moreover we had wonderful discussions about primary education in their villages...
After all those emotional moments one fine day I have decided and made a decision ..
Yes ...I have started trust name called as #Saahasam .
From this trust we want to improve government schools which are located in remote villages. On this aspect we are going to reopen the schools which are closed due to lack of strength and also we are going to provide good education and facilities to those schools .

Consultant at intel

Physical Design Engineer

Dec 2015 – Dec 2016 · 1 yr · Bengaluru Area, India

Here my responsibility towards team is to developing Automation for RTL to GDS flow with sign-off for synopsis and cadence tools.
Develop a new methodology in APR and SIGN-OFF flow.

Consultant at amedrf

Physical Design Engineer

Nov 2015 – Dec 2015 · 1 mo · Bangaloore

Full chip level PNR and PV verification

Consultant at semtech

Physical Design Engineer

Sep 2015 – Oct 2015 · 1 mo · Bhubaneswar

Full chip level Layout verification in 14nm Technology.

Sankalp semiconductor pvt ltd

Physical Design Engineer

Jun 2015 – Dec 2016 · 1 yr 6 mos · Bengaluru Area, India

RTL to GDS

Intel corporation

Internship

Oct 2014 – Jun 2015 · 8 mos · bangloore

I have Completed my Internship in Intel as a full chip clock tree synthesis graduate intern.Here my contribution towards team is ,I have to analyse full chip CTS flow by doing experiments on different stages in clock tree synthesis and recommend the best options for CTS.Along with I have to interact with timing team for ETM models.Here I have done automated script for ETM checks using tcl which generates the clock mismatch attributes and send a XLS report to corresponding mail.
Here I need to say spestial thanks to my mentor and manger Sunil Muralidharan and My buddy Sachin Loher.And I want to say spetial thanks to Sathya for giving me great support during my Internship

Vit university

Graduate Student

Jun 2013 – May 2015 · 1 yr 11 mos · Vellore Area, India

I have done M.tech in VLSI Design at VIT University,Vellore.

Avanthi inistitute of engineering and technology

Undergraduate Student

Jun 2009 – May 2013 · 3 yrs 11 mos · Vishakhapatnam Area,Andhrapradesh,India.

I have done my B.tech in Electronics and Communication Engineering at Avanthi Institute of engineering and technology. Got gold medal from JNTU kakinada .