Hari Krishna Marri

Software Engineer

Bengaluru, Karnataka, India15 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in physical design and timing closure.
Hands-on experience with advanced Place & Route tools.
Proven track record in multi voltage and low power designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Closure.

Contact

Skills

Core Skills

Physical DesignTiming ClosurePlace & Route

Other Skills

ScriptingVLSISoCStatic Timing AnalysisDebuggingICCSOC EncounterMulti Voltage DesignseCosTimingFloorplanningPrimetimeModelSimVerilogTCL

About

 Hands on experience in handling Place & Route tools/Platform like SOC Encounter, NanoRoute, IC Compiler, Sierra Pinnacle, Star-RCXT,Olympus Prime-Time and Calibre.  Hands on with Low power & Multi Voltage designs.  5-10 Tapeout Experience in 28nm/14nm TSMC process.  Good working Knowledge of block level physical design.  Debugging CLP, PV ,PDNA issues  Expertise in closing timing issues with manual fixes in both SI and Non-SI.  Experience in handling high utilized and critical blocks.  Always on the look to improve skills and grow with the organization

Experience

15 yrs 7 mos

Total Experience

5 yrs 2 mos

Average Tenure

13 yrs 8 mos

Current Experience

Qualcomm

3 roles

Staff

Promoted

Dec 2020 – Present · 5 yrs 5 mos

Physical DesignScriptingTiming ClosurePlace & RouteVLSISoC+2

Senior Engineer

May 2015 – Dec 2020 · 5 yrs 7 mos

MSM based Chip: (May'15 - Nov'15)
First 14nm & 100% tile based execution at BDC.
Block level physical design implementation for 2 medium Critical blocks from Netlist to GDSII
& 1 Hierarchical Block PD implementation which also includes FE partitioning of 2 subhm's.
Implementation Tool: ICC & SOC Encounter.

Physical DesignPlace & RouteICCSOC Encounter

Senior Design Engineer

Aug 2012 – Apr 2015 · 2 yrs 8 mos

## Project 5(mobile processor)
no of blocks handle: 3
congestion critical & power collapsible
memory dominant & FT Flow
aggressive leakage targets.
## Project 4 ( Modem related)
# No of Blocks handling : 3
# Block level physical design Implementation from Netlist to GDSII
# Multi voltage designs with CLP checks, PV and PDNA .
# Closing Timing issues with respect to Interface efficiently.
# Used Place & Route tools like SOC Encounter, Olympus, Prime-Time and Calibre.
### Project 3: ( Mobile chip)
No of blocks Handling: 1
# Timing closure for Hard macro which has critical clock gating logic.
# high utilization & setup-hold critical paths
# implementing from PRO DB in ICC Tool.
# Tools used : Prime time,ICC
## Project 2 ( Television)
No of blocks handling : 1
# Block level physical design Implementation from Netlist to GDSII
# Multi voltage designs with CLP checks, PV and PDNA .
# Critical PV lcosure
# Handling Place & Route tools/Platform like SOC Encounter,Olympus, Prime-Time and Calibre.
## Project 1 (Mobile chip)
# No of Blocks handling : 3
# Block level physical design Implementation from Netlist to GDSII
# Multi voltage designs with CLP checks, PV and PDNA .
# Closing Timing issues with respect to Interface efficiently.
# Used Place & Route tools like SOC Encounter, Olympus, Prime-Time and Calibre.