Harshul Mahendroo

Software Engineer

Bengaluru, Karnataka, India7 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI design and physical verification.
Proficient in custom layout design for advanced technology nodes.
Experienced in full chip validation and design verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and ASIC development.

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Skills

Core Skills

Physical DesignVlsi DesignAsic DesignPhysical Verification

Other Skills

Design Rule Checking (DRC)Static Timing AnalysisCustom Layout DesignVerificationFull Chip ValidationFloor PlanningPlacement and RoutingStandard Cell DesignMentor Graphics CalibreCadence VirtuosoCadence Virtuoso Layout EditorVLSI verificationApplication-Specific Integrated Circuits (ASIC)Digital ElectronicsVerilog

Experience

7 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

6 yrs 8 mos

Current Experience

Intel corporation

2 roles

Physical Design Integration Engineer

May 2021 – Present · 5 yrs

Physical DesignDesign Rule Checking (DRC)Static Timing AnalysisPhysical VerificationVLSI Design

SoC Design Engineer

Sep 2019 – May 2021 · 1 yr 8 mos

Layout Design Engineer with experience in design and verification of standard cells, System on Chip design - top level to block level and Full Chip design, validation and Tape-in related activities.
Area of Expertise:
▪ Custom Layout Design & Verification for 90nm, 22nm, 10nm, 7nm, 5nm and lower technology nodes.
▪ Exposure in Testchip development & its components, Full Chip Validation and various other Tape-in related activities.
▪ Experience in custom design and verification for different types of testchips & its components, Analog circuits- Aging circuits, POR Circuits, multidimensional structures and Digital circuits based on electromigration, biased temperature stressing, ESD, RF
structures and standard cells.
▪ Experience in Floor Planning, Placement and Routing and improving Cell Congestion.
▪ Expertise in Physical design verification at top level and block level integration.

Custom Layout DesignVerificationFull Chip ValidationFloor PlanningPlacement and RoutingVLSI Design+1

Stmicroelectronics

Layout Design

Jan 2019 – Jul 2019 · 6 mos · Noida Area, India

Standard Cell Design and Validation
Familiar with Mentor Graphics Calibre and UNIX environment.
Layout Design (Standard Cell Library) for technologies nodes like 90nm, 40nm, 28nm.
Proficient with Cadence Virtuoso and Eldo Optimizer.
Experience in various physical verification checks like DRC, LVS, ESD, DFM, etc.
Experienced in resolving various:
DRC violations like off grid checks, via/metal layer spacing, via/metal layer enclosure, PR boundary violations, etc.
DFM issues like PnR routing grid, congestion and area issues.
LVS violations like incorrect ports, discrepancies, etc.
Good Understanding of Digital Design Logic and ASIC digital design flow.
Balanced Clock Tree Cells development for standard cell library.