Jaimeen S.

Program Manager

Bengaluru, Karnataka, India15 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 12 years of experience in Signal & Power Integrity.
Expert in IBIS-AMI modeling for high-speed interfaces.
Strong leadership in managing sizable SIPI teams.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on Signal Integrity and Power Integrity.

Contact

Skills

Core Skills

Strategic Project ManagementLeadershipSipiTeam LeadershipSignal IntegrityIbis

Other Skills

People ManagementStrategic PlanningIntellectual Property ManagementChipletsMentoringCross-functional Team LeadershipPower IntegritySignal ProcessingMixed-Signal IC DesignTeamworkTeam ManagementTeam BuildingIBIS-AMISerDesD2D

About

Moved to new Role as Program manager for Qualcomm Core IPs. SIPI and IBIS and IBIS-AMI modelling Engineer. Jaimeen is a seasoned Signal & Power Integrity Engineer with over 12 years of experience at Qualcomm. He possesses extensive expertise in system-level full channel simulation for high-speed interfaces such as SerDes and DDR. He has been instrumental in developing methodologies and sign-off simulations for Chip-lets SIPI DoE in 2.5D/3D PKG technology. He successfully created the IBIS-AMI generation flow for both SerDes and DDR interfaces from scratch at Qualcomm. His experience spans various form factor applications across platforms including Mobile, Automotive, IoT, Compute, and Data Centers. Jaimeen leads a sizable SIPI team, demonstrating strong leadership and team development skills.

Experience

15 yrs 11 mos

Total Experience

3 yrs 2 mos

Average Tenure

12 yrs 6 mos

Current Experience

Qualcomm

7 roles

Senior Program Manager

Promoted

Feb 2026 – Present · 3 mos · On-site

Modem IP

Strategic Project ManagementPeople ManagementLeadershipStrategic PlanningIntellectual Property Management

Senior Staff Engineer/Manager

Nov 2025 – Feb 2026 · 3 mos · On-site

SIPIChipletsTeam LeadershipMentoringCross-functional Team Leadership

Staff Engineer/Manager

Jun 2023 – Nov 2025 · 2 yrs 5 mos · On-site

Signal IntegrityPower IntegritySIPISignal ProcessingMixed-Signal IC DesignLeadership+11

Staff Engineer

Dec 2021 – May 2023 · 1 yr 5 mos · On-site

Signal IntegrityPower IntegritySIPIMixed-Signal IC DesignIBIS

Senior Lead Engineer

Dec 2018 – Nov 2021 · 2 yrs 11 mos · On-site

IBIS and IBIS-AMI models generation and validation for all interfaces [GPIOs, CustomIOs, DDR IOs, all SERDES]
SI & PI analysis for DDR and SERDES interfaces
Board and Package signal S-parameter extraction using PowerSI, Ansys HFSS
Via modelling using Ansys HFSS

Senior Engineer

Jun 2016 – Nov 2018 · 2 yrs 5 mos · On-site

IBIS and IBIS-AMI models generation and validation for all interfaces [GPIOs, CustomIOs, DDR IOs, all SERDES]
Package RLC extraction using Q3D
Chip level IBIS models
Setup RX AMI models generation flow for DFE

Engineer

Jul 2013 – May 2016 · 2 yrs 10 mos · On-site

IBIS and IBIS-AMI models generation and validation for all interfaces [GPIOs, CustomIOs, DDR IOs, all SERDES]
Setup flow to generate .so file for AMI models to support Linux based simulation [dll file is used for window based simulation]
Setup AMI models generation flow for both transmitter and receiver [de-emphasis, pre-emphasis, CTLE, FFE]
Creating and modifying Schematic based on requirement and generate STAR-RC netlist to generate IBIS models