Jatinkumar Koshiya — Software Engineer

💌 Invites / Collaborations: hardwareexpert14@gmail.com Current Role: Senior Design Verification Engineer at Microsoft, part of the Artificial Intelligence System on Chip (AISoC) Silicon team. I contribute to verifying cutting-edge designs that power the next generation of AI applications and building AI Copilots/applications which improves productivity of DV engineers in DV life cycle. Academic Background: • Master’s in VLSI Design • Bachelor’s in Electronics and Communication Engineering • Both degrees from Nirma University, India Core Competencies: • SoC & IP Verification • SystemVerilog, UVM, and advanced verification methodologies • AI Hardware, GPU, SmartNIC, and Network Processor verification • Constraint Random Verification and Performance/QoS Verification • Protocols: Ethernet, AMBA AXI4, APB • Tools: VCS, Verdi, Synopsys simulators, Perl/Shell scripting Professional Experience: • Successfully verified multiple IPs and super blocks at Microsoft, NVIDIA, and Intel • Built and integrated reference models, test benches, and coverage-driven environments • Worked with third-party VIPs and industry-standard communication protocols Knowledge Sharing & Recognition: • Passionate about mentoring and guiding aspiring engineers • Recognized with multiple awards for contributions and performance • Active content creator and educator in the VLSI/DV space Mentorship Promise: I’m committed to helping the next generation of engineers succeed. Whether you're a fresher or an experienced professional, I offer personalized guidance on: • VLSI/DV career paths • Interview preparation & mock interviews • Resume & LinkedIn profile reviews • Long-term mentorship and career planning Book a 1:1 Session: • Topmate: https://topmate.io/jatinkoshiya • Preplaced (Long-term mentorship): https://preplaced.in/profile/jatin-koshiya • CodeMentor: https://www.codementor.io/@hardwareexpert • MentorCruise: https://mentorcruise.com/mentor/jatinkoshiya/ YouTube Channel: • Subscribe to VLSI with Jatin: https://www.youtube.com/@VLSIwithJatin Contact: • For collaborations or queries: hardwareexpert14@gmail.com Personal Portfolio: https://jatin-koshiya-tgrdc8f.gamma.site/ ***All views expressed are my own and do not reflect those of my employer.***

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in AI hardware and design verification.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 7 mos

Skills

Functional Verification
Systemverilog
C++

Career Highlights

Spearheaded AI initiatives enhancing design verification productivity.
Mentored aspiring engineers with personalized guidance.
Recognized with multiple awards for contributions and performance.

Work Experience

Microsoft

Senior Design Verification Engineer (1 yr 3 mos)

Design Verification Engineer 2 (1 yr 8 mos)

NVIDIA

Senior Verification Engineer (2 mos)

Intel Corporation

Senior Verification Engineer (3 yrs 9 mos)

Verification Engineer (2 yrs 9 mos)

Tata Consultancy Services

Assitant Systems Engineer (1 yr 11 mos)

The Maharaja Sayajirao University of Baroda

Student Internship (0 mo)

Education

Master of Technology - MTech at Nirma University

Bachelor of Technology - BTech at Nirma University

Higher Secondary School at Shree Sardar Patel Vidhyalaya, Surendranagar, Gujarat,India

Jatinkumar Koshiya

Software Engineer

Bengaluru, Karnataka, India8 yrs 7 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Spearheaded AI initiatives enhancing design verification productivity.
Mentored aspiring engineers with personalized guidance.
Recognized with multiple awards for contributions and performance.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in AI hardware and design verification.

Contact

Skills

Core Skills

Functional VerificationSystemverilogC++

Other Skills

Python (Programming Language)Problem SolvingUVMPerlMicrosoft Visual Studio C++CGI StudioYAMLGitHub CopilotMicrosoft Visual Studio CodeGenerative AIGenerative AI ToolsAI HardwareGPUSmartNICNetwork Processor verification

About

Experience

8 yrs 7 mos

Total Experience

2 yrs 10 mos

Average Tenure

2 yrs 11 mos

Current Experience

Microsoft

2 roles

Senior Design Verification Engineer

Promoted

Mar 2025 – Present · 1 yr 3 mos · Hybrid

Spearheaded AI initiatives in Design Verification at Microsoft, enhancing team productivity through innovative solutions.
Developed and integrated M365 Copilot Agent and AI agents into design workflows, streamlining processes.
Leveraged tools like VS Code and GitHub Copilot to optimize design verification tasks, resulting in significant time savings.

Functional VerificationPython (Programming Language)

Design Verification Engineer 2

Jun 2023 – Feb 2025 · 1 yr 8 mos · Hybrid

Collaborated with the Microsoft AISoC Silicon team to build and verify cutting-edge AI chips.
Spearheaded stub-based verification processes at the SoC level, enhancing efficiency and accuracy.
Developed and executed comprehensive CPP tests using YAML parameters, resulting in improved regression outcomes.
Engaged in rigorous debugging, contributing to a more robust AI chip architecture.

Functional VerificationSystemVerilog

Nvidia

Senior Verification Engineer

Apr 2023 – Jun 2023 · 2 mos · Bengaluru, Karnataka, India · Hybrid

Spearheaded unit-level verification for the memory subsystem in NVIDIA's cutting-edge GPU projects.
Conducted performance verification, ensuring optimal functionality and efficiency of GPU components.
Collaborated with cross-functional teams to enhance verification processes, leading to improved product reliability.

SystemVerilogProblem Solving

Intel corporation

2 roles

Senior Verification Engineer

Promoted

Jun 2019 – Mar 2023 · 3 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

▪ Project: Mount Morgan IPU (Intel Infrastructure Processing Unit) (SmartNIC)
▪ Reference model component development for out-of-order packet flit received from AXI4 stream and
end to end scoreboard of packets
▪ Experience in leading packet processing IP verification and class of service queue IP verification from testplan development to coverage closure
▪ Single-handed drove TFM (Tool Flow Methodology) related activities at multiple IP.
▪ Developed Perl script for generating directed regression test suite for functional verification of packet processing IP.
▪ Trained multiple interns joined the team with SystemVerilog, UVM methodology and functional verification.

SystemVerilogUVM

Verification Engineer

Jun 2019 – Mar 2022 · 2 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

▪ Project: Mount Evans IPU (Intel Infrastructure Processing Unit)
▪ Product Link: https://www.intel.com/content/www/us/en/products/details/network-io/ipu/adapter-e2100.html
▪ Successfully lead and completed packet processing IP level Unit and features verification from architecture understanding, testplan creation, environment infrastructure update, testbench component
development, test scenario and sequence creation, checkers, test running and debugging with designers or at subsystem level, regression, triage and coverage closure
▪ Have done Hysteresis feature verification for pipe monitor and raised multiple bugs to designer
▪ Having experience in networking ethernet protocol and AMBA AXI4, APB communication protocol.
▪ Hands on experience with verification tools such as VCS, Verdi waveform analyzer and third-party VIP integration (such as Synopsys VIPs).
▪ Expertise in constraint random function verification and Performance-QoS verification of multiple IPs in SystemVerilog and UVM based testbench environment
▪ Having good understanding of SystemVerilog Assertions, Low Power Verification using UPF and Power Analysis of RTL using PowerArtist (Ansys tool).
▪ 1-year full time internship experience in Design Verification team in Hardware accelerator IP.

Microsoft Visual Studio C++C++

Tata consultancy services

Assitant Systems Engineer

Aug 2016 – Jul 2018 · 1 yr 11 mos · Pune Area, India

▪ Project: In-Vehicle Infotainment (IVI) Development
▪ Role: UI (User Interface) Developer with CPP model development
▪ Environment/Skills: CGI Studio, Visual Studio, C++
▪ Based on MVC (Model – View – Controller) architecture, developed the user interface using CGI studio and C++ model development.
▪ Developed C++ model of IVI system to verify the system and deployed it at Embedded system for verification with multiple testcase.
▪ Created and verified multiple scenarios based on MVC architecture specifications for bug free system delivery.
Awards:
1) Received On the Spot Award for solving critical problems at the time of Project deliveries.
2) Received Champions of ILP Award for best performance and helping freshers at the time of the Initial Learning program (ILP).

The maharaja sayajirao university of baroda

Student Internship

Jan 2011 – Jan 2011 · 0 mo · Vadodara Area, India

Participated in Innovation in Science Pursuit for Inspired Research (INSPIRE) camp during 17-21th January 2011 organized by Applied Physics Department, Faculty of Engineering and Technology, The M. S University of Baroda, Vadodara.