Jerin Varghese — Product Engineer

Experienced DFT (Design for Test) Engineer with expertise in scan insertion, ATPG, and post-silicon test methodologies for complex SoCs. Proficient in industry-standard tools and scripting, with a strong focus on improving test coverage and silicon quality. Key Skills & Expertise: • Scan Insertion & Stitching: Hands-on experience with Mentor Tessent Scan, Design Compiler for RTL-to-GDS scan flow. • EDT Compression: EDT IP insertion and synthesis using Mentor TestKompress and FastScan in both compression and bypass modes. • ATPG Pattern Generation & Debug: Extensive ATPG for Stuck-at, Transition, Cell-Aware, Bridging, and IDDQ faults using Tessent FastScan and Synopsys TetraMAX. • Verification & Debug: DRC verification, SSN, ICL, PDL generation and validation. Experience in GLS verification using VCS, Verdi, Cadence Xcelium, and Questa Sim. • Scripting & Automation: Strong scripting skills in Shell, Python, and Perl for test automation, reporting, and regression management.

Stackforce AI infers this person is a DFT Engineer specializing in VLSI and SoC testing methodologies.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 1 mo