Khushboo Harlalka — Software Engineer

Experienced RTL Design Engineer with an excellent track record in the Micro-architecture & RTL design At Google, I excelled in microarchitecture development and writing power-efficient RTL, leading to improved performance and project outcomes. I automated joules-level power tracking across flows, drove convergence of lint, CDC, and RDC, and closely collaborated with architecture and DV teams to ensure timely bug resolution and coverage closure. Prior to this, I pioneered the development of Xilinx RFSoC-based radar signal processors, beam steering networks, and firmware for critical radar subsystems. My work has directly contributed to six deployed defence systems and includes: Developing high-speed FPGA-based signal processors Inventing a remote FPGA programming technique without external microcontrollers Building timing and digital receiver modules for QRSAM RADAR Authoring 1 patent, 1 copyright, and 4 international publications I am deeply passionate about designing reliable, power-aware digital systems that scale from concept to silicon. I bring a unique blend of product mindset, RTL depth, and system-level thinking, with a strong focus on collaboration, ownership, and quality. 🔍 Current Focus: Technical growth in SoC integration, low-power design, and formal-driven RTL development — in an environment that values innovation. Let’s connect if you’d like to collaborate on high-impact digital design!

Stackforce AI infers this person is a Semiconductor and Defense industry expert with a focus on RTL design and system integration.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 7 mos