K

K.Sai Rameswari

Software Engineer

Bengaluru, Karnataka, India9 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC and Physical Design.
  • Proficient in multiple verification methodologies.
  • Strong background in semiconductor engineering.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

AsicPhysical DesignVerification

Other Skills

VerilogSystemVerilogCPerlTCLSynopsys toolsFPGAUniversal Verification Methodology (UVM)Low-power DesignJTAGAPB interface

Experience

9 yrs 5 mos
Total Experience
3 yrs 6 mos
Average Tenure
7 yrs 2 mos
Current Experience

Samsung semiconductor

3 roles

Senior Staff Engineer

Promoted

Mar 2024 – Present · 2 yrs 3 mos

VerilogSystemVerilogCPerlASICTCL+5

Staff Engineer

Mar 2022 – Mar 2024 · 2 yrs

Associate staff Engineer

Mar 2019 – Feb 2022 · 2 yrs 11 mos

Amd

Contractor

Apr 2017 – Jun 2018 · 1 yr 2 mos · banglore

Graphene semiconductor services pvt ltd.

Verification Engineer

Dec 2016 – Mar 2019 · 2 yrs 3 mos · Bangaon Area, India

  • Verification of PVT Sensor using JTAG and APB interface

Education

Jawaharlal Nehru Technological University Kakinada

Master's Degree — VLSI Design

Jan 2013 – Jan 2015

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