Madhur Maheshwari — Software Engineer

Working now as Senior Lead DFT Engineer in DSP team at Qualcomm. Worked at AMD as a Senior Silicon Design Engineer in the DFT team, driving end-to-end DFT implementation for multiple IPs. My work spans scan insertion, ATPG, timing simulation debug, and production pattern delivery, while automating flows to improve efficiency and coverage targets. Worked as Product Validation Engineer at Cadence Design System, Noida. Skilled in Digital electronics, DFT, ATPG, Verilog, scripting in Perl. Working on Modus(Cadence tool). Knowledge about DFT technologies (Compression, Boundary Scan, JTAG, LBIST) Graduated from YMCA University, Faridabad in 2019 with a good academic record.

Stackforce AI infers this person is a DFT and silicon design expert in the semiconductor industry.

Location: Faridabad, Haryana, India

Experience: 6 yrs