Mohadin H B — Director of Engineering

Dedicated VLSI professional with over 18+ years in semiconductor design and engineering. Expertise in developing and leading multidisciplinary teams, successful implementation of strategic initiatives, and driving innovative solutions. Work Experience Summary: Standard/IO Cell Library Development : Specialized in circuit & layout design, Expertise in modeling all frontend & backend views which are critical to the RTL2GDS flow. Implemented Primetime versus spice correlation flows for delays QA. Worked with Design teams/Tool/Foundries to discuss about PDK Kits, tool/Flow enhancements. Involved in FRS creation/Project and resource management. SoC Logic Synthesis and LEC Flow Development : Developed efficient SOC flow methodologies for various process nodes ensuring design quality and efficiency. Focused on high-performance designs, ensuring logical equivalence throughout the development process, TCL scripting/automation for large SOC blocks. benchmarking studies on different libraries to optimize PPA metrics for SOC designs. Developed Synthesis, LEC methodology and CAD support to design teams, resolving technical issues and driving process improvements, supported various design teams for ASIC blocks to close functionality between RTL to SYN/PNR netlists. UPF, CLP Flows development and technical support for various process nodes till 3nm nodes for ASIC and custom blocks. Frontend Digital Implementation : Block design services which includes LINT, Concert/Conman, CDC, and SDC verification on RTL designs. Executed logic synthesis to meet Power, Performance, and Area (PPA) targets. Engaged in functional verification using the Conformal LEC tool. Handled scan cell logic insertion and STA/ timing signoff using primetime, ensuring successful netlist delivery to the physical design (PD) team. RTL Integration for Modem Subsystems : Led a team in running all frontend checks (CDC, LINT, SDC, synthesis, LEC, CLP, STA) on modem subsystems. Managed RTL integration team and ensured seamless functionality. Demonstrated strong team management, managing a team of 15+ team members with effective resource and technical management. SerDes/UCIe/USB PHY QA and Release Activities : Delivered high-quality products consistently through effective QA and release management. Fostered collaboration across cross-functional teams. Leadership & Team Management : Built and led a team from the ground up, effectively managing over 15+ members. Demonstrated strong resource and technical management skills, fostering a collaborative environment that drove successful project outcomes.

Stackforce AI infers this person is a VLSI Design and Engineering expert with extensive experience in semiconductor design.

Location: Bengaluru, Karnataka, India

Experience: 18 yrs 2 mos