Mukesh Kumar

Software Engineer

Udupi, Karnataka, India22 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in standard cell library analysis and design.
Proficient in CMOS circuit design and transistor fabrication.
Extensive experience in high-speed library development.

Stackforce AI infers this person is a semiconductor design engineer specializing in standard cell library development.

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Skills

Core Skills

Standard Cell Library DevelopmentStandard Cell Library Analysis

Other Skills

validationcharacterization of standard cell librarytechnical assistancestdcell library analysislevel-shifter designfinfet standard cell library designCMOS circuit designtransistor fabrication processhigh-speed multivt libraryring oscillator layoutsCadence toolCadabra toolDFM and ESD

Experience

22 yrs 5 mos

Total Experience

7 yrs 5 mos

Average Tenure

11 yrs 9 mos

Current Experience

Synopsys

R & D Engineer

Sep 2014 – Present · 11 yrs 9 mos · Bangalore

Working on standard cell library development as part of build and validation group in Synopsys.

standard cell library developmentvalidation

Amd

Member of techinal staff, AMD india pvt ltd

Dec 2010 – Sep 2014 · 3 yrs 9 mos · Bangalore

1) Characterization of standard cell library for in-house customers and providing technical assistance on the custom needs.
2) Expert in stdcell library analysis for stability/race/Charge-sharing/MTBF/SER.
3) Level-shifter design and analysis for standard cell library.
4) Trained on finfet standard cell lirary design.

characterization of standard cell librarytechnical assistancestdcell library analysislevel-shifter designfinfet standard cell library designstandard cell library analysis

Karmic manipal

Member of Technical staff

Jan 2004 – Dec 2010 · 6 yrs 11 mos · Manipal

1) Training on CMOS circuit design and transistor fabrication process.
2) Worked in all aspects of a standard cell library development and have an indepth
knowledge of it. Provided consultation on library development and support.
2) Responsible for developing and delivering a high speed, multivt
library.
3) Worked on development of ring oscillator Layouts for 32nm node to detect device
and interconnect process variation.
4) Worked on Cadence tool viz icfb
5) Worked on Cadabra tool for generation of layouts for a digital library.
6) Currently supporting 45nm high performance library and working on the design
and layouts of 28nm library.
7) Worked on Architecture cell's development of 45nm library for DFM and ESD.