Muthia Ms

Software Engineer

Bengaluru, Karnataka, India22 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design Implementation and Verification.
Proficient in Low Power Design and IR Drop Analysis.
Extensive experience in Logical Equivalence Checking methodologies.

Stackforce AI infers this person is a Semiconductor Design Expert with a focus on Physical Design and Verification.

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Skills

Core Skills

Physical DesignClock Tree SynthesisLogical Equivalence CheckingPower Analysis

Other Skills

Conformal LECLow power conceptsCPFIR drop analysisConformal Low power toolRedhawkUPFASICSoCLogic SynthesisTiming ClosureVLSILow-power DesignSemiconductorsCMOS

About

Specialties: Physical Design Implementation, Floorplaning, PnR, ECO implementation, Logical Equivalence checking, CPF concepts, development and verification, IR drop Analysis, Constraints and Netlist Screening, Digital Simulation

Experience

22 yrs 8 mos

Total Experience

7 yrs 6 mos

Average Tenure

11 yrs 8 mos

Current Experience

Broadcom

Principal Engineer

Oct 2014 – Present · 11 yrs 8 mos · Bangalore

Clock Tree SynthesisConformal LECPhysical Design

Qualcomm

Sr Lead Engineer

May 2012 – Oct 2014 · 2 yrs 5 mos · India

Nxp semiconductors india pvt limited

2 roles

Technical Leader

Oct 2006 – Apr 2012 · 5 yrs 6 mos

Working on the Logic Equivalence checking, Low power concepts using CPF and verification of CPF using Conformal Low power tool.
IR drop analysis using Redhawk (dynamic and static) for STB and TV SoCs.
Past Experience:
Design Methodology development: Have developed flows for Logical Equivalence checking, Constraints Screening, Netlist Screening, Simulation and IR drop Analysis.

Logical Equivalence checkingLow power conceptsCPFIR drop analysisPower Analysis

Senior Design Engineer

Sep 2003 – Oct 2006 · 3 yrs 1 mo

I was working in Design Methodology team. Which was developing flows and methodologies for ASIC design. Worked in development of Simulation, Logical Equivalence checking, Screening and Logic Synthesis methodology and flows.