Parthabi Padhi — Software Engineer
I am a Design Verification Engineer with a Master’s degree in VLSI Design and 4 years of hands-on industrial experience in the design verification domain. I have background knowledge on module, subsystem, and SoC verification. My expertise includes: Verification Methodologies: Proficient in Verilog, SystemVerilog, and UVM. Simulation: Experienced in gate-level simulations to ensure robust design integrity. I am passionate about leveraging my skills to tackle complex verification challenges and contribute to cutting-edge projects in the industry.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in UVM and design integrity.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 4 mos
Skills
- Universal Verification Methodology (uvm)
Career Highlights
- 4 years of experience in design verification.
- Proficient in UVM, Verilog, and SystemVerilog.
- Expertise in gate-level simulations for design integrity.
Work Experience
MaxLinear
Design Verification Engineer (3 yrs 5 mos)
NVIDIA
Design Verification Engineer - Consultant from FrenusTech Pvt Ltd. (1 yr)
FrenusTech Pvt Ltd
Design Verification Engineer (11 mos)
Trainee (2 mos)
Maven Silicon
RTL Design and Verification trainee at Maven Silicon (7 mos)
Education
Master's degree at Veer Surendra Sai University Of Technology ( Formerly UCE ), Burla
Bachelor's degree at Gandhi Engineering College (GEC), Bhubaneswar
High School at Kendriya Vidyalaya Khurda Road
