Pooja Kumawat — Software Engineer

🎯With a career rooted in the semiconductor industry, I bring specialized expertise in 𝘗𝘰𝘸𝘦𝘳 𝘔𝘰𝘥𝘦𝘭𝘪𝘯𝘨 𝘢𝘯𝘥 𝘈𝘯𝘢𝘭𝘺𝘴𝘪𝘴, 𝘗𝘩𝘺𝘴𝘪𝘤𝘢𝘭 𝘈𝘸𝘢𝘳𝘦 𝘚𝘺𝘯𝘵𝘩𝘦𝘴𝘪𝘴, 𝘍𝘭𝘰𝘰𝘳-𝘱𝘭𝘢𝘯𝘯𝘪𝘯𝘨, 𝘗𝘭𝘢𝘤𝘦𝘮𝘦𝘯𝘵, 𝘊𝘛𝘚, 𝘙𝘰𝘶𝘵𝘪𝘯𝘨, 𝘚𝘵𝘢𝘵𝘪𝘤 𝘛𝘪𝘮𝘪𝘯𝘨 𝘈𝘯𝘢𝘭𝘺𝘴𝘪𝘴, 𝘙𝘦𝘭𝘪𝘢𝘣𝘪𝘭𝘪𝘵𝘺 𝘝𝘦𝘳𝘪𝘧𝘪𝘤𝘢𝘵𝘪𝘰𝘯 (𝘌𝘔, 𝘐𝘙, 𝘕𝘰𝘪𝘴𝘦), 𝘗𝘩𝘺𝘴𝘪𝘤𝘢𝘭 𝘝𝘦𝘳𝘪𝘧𝘪𝘤𝘢𝘵𝘪𝘰𝘯 𝘧𝘰𝘳 𝘍𝘶𝘭𝘭 𝘊𝘩𝘪𝘱 𝘢𝘯𝘥 𝘉𝘭𝘰𝘤𝘬, 𝘓𝘌𝘊, 𝘛𝘊𝘓 𝘢𝘯𝘥 𝘗𝘦𝘳𝘭 𝘢𝘯𝘥 𝘗𝘺𝘵𝘩𝘰𝘯 𝘚𝘤𝘳𝘪𝘱𝘵𝘪𝘯𝘨 across high-performance projects at 𝗡𝗩𝗜𝗗𝗜𝗔, 𝗜𝗻𝘁𝗲𝗹, 𝗮𝗻𝗱 𝗡𝗫𝗣 𝗦𝗲𝗺𝗶𝗰𝗼𝗻𝗱𝘂𝗰𝘁𝗼𝗿𝘀. My experience spans multiple facets of Chip Design and Verification, with a consistent focus on enhancing Performance, Efficiency, and Reliability in complex systems. 👉 Currently at 𝗡𝗩𝗜𝗗𝗜𝗔, I focus on Power Modeling and Analysis to enhance efficiency and reliability in next-gen products. 👉 At 𝗜𝗻𝘁𝗲𝗹, I worked on SOC RTLFP, Top Level Interconnect Planning, Physical Design & Verification, Reliability verification(EM, IR) and Design Automation in the Xeon Engineering Group. 👉 My role at 𝗡𝗫𝗣 𝗦𝗲𝗺𝗶𝗰𝗼𝗻𝗱𝘂𝗰𝘁𝗼𝗿𝘀 involved SRAM compiler design, conducting Bitcell analysis, DC offset studies, Timing/Leakage Measurements, and Static Noise Margin Analysis. Driven to advance semiconductor technology through innovation in power efficiency and robust chip design. The more I learn, the more I want to Learn !!

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Power Efficiency and Chip Design.

Location: Jaipur, Rajasthan, India

Experience: 3 yrs 8 mos