Prasoon Jain

CEO

India24 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in IC design with extensive experience in physical design.
Proficient in VLSI and ASIC methodologies.
Strong background in RTL design and EDA tools.

Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on physical design in the semiconductor industry.

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Skills

Other Skills

SoCStatic Timing AnalysisVerilogVHDLVLSIASICSemiconductorsRTL designEDAPhysical Design

Experience

24 yrs 8 mos

Total Experience

3 yrs 1 mo

Average Tenure

3 yrs 10 mos

Current Experience

Intel corporation

IC design

Jul 2022 – Present · 3 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Nordic semiconductor asa

Senior R&D engineer

Aug 2018 – Jun 2022 · 3 yrs 10 mos · Trondheim Area, Norway · On-site

Physical design and implementation

Intel corporation

2 roles

Staff physical design engineer/Engineering manager

Aug 2016 – Jul 2018 · 1 yr 11 mos

Structural and physical design

Staff physical design Engineer/Engineering Manager

Jan 2013 – Jul 2016 · 3 yrs 6 mos

Structural and physical design

Stericsson asia pacific

Staff design engineer

Dec 2011 – Dec 2012 · 1 yr · Singapore

Stmicroelectronics

Engineering specialist

Apr 2007 – Nov 2011 · 4 yrs 7 mos · Bangalore

Nvidia graphics pvt. ltd.

senior engineer

Jan 2005 – Jan 2007 · 2 yrs

Cypress semiconductor

staff engineer

Jan 2003 – Jan 2005 · 2 yrs

Tata elxsi

senior engineer

Jan 2001 – Jan 2003 · 2 yrs

Education

Centre for Development of Advanced Computing (C-DAC)

Diploma in VLSI design — VLSI

Jan 2000 – Jan 2000

Shri G S Institute of Technology & Science

BE — Electronics & Telecommunications

Jan 1995 – Jan 1999

L.O.T.I.

Jan 1991 – Jan 1995

Stackforce found 100+ more professionals with SoC & Static Timing Analysis

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