Raj kumar

Software Engineer

San Jose, California, United States6 yrs 6 mos experience

Most Likely To Switch

Key Highlights

Expert in Digital ASIC Design and Verification.
Proficient in EDA tools and Physical Design methodologies.
Strong foundation in Hardware Description Languages and Scripting.

Stackforce AI infers this person is a Digital ASIC Design Engineer with expertise in EDA tools and Physical Design.

Contact

Skills

Core Skills

Physical DesignEda

Other Skills

Physical VerificationECOStatic Timing AnalysisClockingTimingScriptingVerilogVHDLTCLLinuxMicrosoft OfficeXilinx VivadoManagementPublic SpeakingSynopsys ICC

About

Digital ASIC Design and Verification enthusiast, focusing on back-end Physical Design. Skills: • EDA Tools : Cadence NCLaunch, Cadence Genus, Cadence Tempus, Cadence Innovus, Cadence Virtuoso, Xilinx ISE, ModelSim • Hardware Description Languages : Verilog, VHDL • Scripting Languages : TCL • Hardware Platforms : Artrix-7 Nexys-4 DDR FPGA • Operating System : Linux, Windows • Software Packages : Microsoft Office Suite

Experience

6 yrs 6 mos

Total Experience

1 yr 7 mos

Average Tenure

3 yrs

Current Experience

Tsmc

Design Engineer

Jun 2023 – Present · 3 yrs · San Jose, California, United States · Hybrid

EDAPhysical DesignPhysical VerificationECOStatic Timing Analysis

University of southern california

Graduate Teaching Assistant

Jan 2023 – Apr 2023 · 3 mos · Los Angeles, California, United States

Amd

Intern - Physical Design

May 2022 – Dec 2022 · 7 mos · Santa Clara, California, United States

ClockingTimingScriptingPhysical Design

Blr labs pvt. ltd.

ASIC Physical Design Engineer

Jan 2019 – Jul 2021 · 2 yrs 6 mos · Bengaluru Area, India

ClockingTimingScriptingPhysical Design

Entuple technologies pvt. ltd.

Probationary Trainee Engineer - Physical Design

Jul 2018 – Dec 2018 · 5 mos · Bengaluru, Karnataka, India

ClockingTimingScriptingPhysical Design

Sandeepani- school of embedded system design

Internship on Designing with FPGA

Jan 2018 – Jan 2018 · 0 mo · Bangalore, India

Advanced Digital Design
Introduction to registers and counters
Synchronous Finite State Machine Design
Data-path elements - Arithmetic Structures
Introduction to Programmable Platforms
Design Capture and Simulation
Practical Digital System Design Examples
Verilog
Hardware Modeling Overview
Verilog language concepts
Modules and Ports
Dataflow Modeling
Introduction to Test benches
Operators
Procedural Statements
Controlled Operation Statements
Coding for Finite State Machines
Coding For Synthesis
FPGA
FPGA Design Flow - Xilinx Vivado tool Flow, Reading Reports
Optimal FPGA Design - HDL Coding Techniques for FPGA,
FPGA Design Techniques, Synthesis Techniques, Implementation Options on Zynq- Boards

Entuple technologies pvt. ltd.

2 roles

Short term course on Analog IC Design - Circuit and Layout Design Methodologies

Dec 2017 – Dec 2017 · 0 mo

Analog IC Design - Circuit and Layout Design Methodologies using Cadence Analog Design Flow.
Analyze the performance specification requirements and identify the suitable circuit topologies
PDK Device Characterization for Analog Model Parameters
TSynthesize basic and OP-AMP amplifier circuit topologies
Design CMOS Amplifier circuits for given DC and AC performance parameters
Develop programmed spread sheets for amplifier design automation
Design and Performance characterization of CMOS Current Mirror (Schematic Design and Simulation)
DC performance characterization of the Basic CMOS Differential Amplifier (5 pack OP-AMP)
Design and Characterization of the CS Amplifier for small signal DC and AC performance
Design and Characterization of Differential pair for small signal DC and AC performance
Design and characterize a seven-pack CMOS compensated OP-AMP at the schematic design entry level
Derive layout constraints for the physical design of the OP-AMP and carry out DRC and LVS
Carry out the physical verification and parasitic extraction
Back Annotate and carry out Post Layout Simulation/ Characterization

Short Term Course on Fundamentals of Physical Design & Verification using Cadence Tool Flow

Dec 2017 – Dec 2017 · 0 mo

Getting started with Cadence RTL Compiler & SOC Encounter tools
Functional Simulation and syntesis of the given design
RTL synthesis of a given design block (Gate level simulation)
Analysis of individual blocks of a design
Netlist and Floor planning
Placement
Routing
Physical verification
Static timing analysis of verified design

Research & development establishment (r&d(engrs)), drdo

Summer Internship

Jun 2017 – Jul 2017 · 1 mo · Pune Area, India

Training on characterization of Proximity Sensors
Project: Analysis of proximity sensor for applications specified in the field of defense

ClockingPhysical Design

Crisp

Training Course on VLSI Design

Jun 2016 – Jul 2016 · 1 mo · Bhopal Area, India

Front-end & Back-end VLSI design styles
Electronic Design Automation Tools (Xilinx, Dsch, Microwind)
CMOS circuit designing, Standard Cell Layout Design, and Verification using DRC
Digital Circuit Design using VHDL, and Implementation on programmable chips (FPGA's)