Mar 2015 – Mar 2018 · 3 yrs

May 2013 – Dec 2014 · 1 yr 7 mos · Bengaluru Area, India

• I had worked on TI's driver design for 90 nm flash process. As part of this effort, I had worked on:
• Defining the Test, Verification, and DFT specification for this design. This includes: standard structural tests with scan methodology, memory tests using memory BIST, and memory repair solutions for repairable memories.
• Generation of structured test, and memory BIST patterns. Validation of these patterns at various corners / operating conditions.
• Generation and validation of IDDQ test patterns. This includes both logic and memory IDDQ. Generation and validation of memory retention test patterns. Also generation and validation of Burn-in patterns
• Defining Test, Verification, and DFT methodology for few of the IP’s contained in it: AVDAC, ADC, Camera_rx PHY. All of these IP’s are self contained hard macros. They all have IEEE 1500 controller to place these IP’s in various functional/structured test modes. The functional tests include loopback, and other characterization tests. These IP’s also support extest modes in which the interface between the IP and the SoC is also tested.
• Post silicon debug which contains understanding of the tester log file and mapping the failures back to the TDL. Also provided new set of patterns to pin point the actual failures.

Feb 2012 – Apr 2013 · 1 yr 2 mos · Bengaluru Area, India

• I had worked on DFT, and Test aspects of 28 nm, and 40 nm versions of DDR. The DDR IP available in these nodes do not have external communication interface. There is also no BIST engine available as part of the DDR cmd_phy. In order to be able to completely test this IP, I have developed the following solutions around this IP. These include:
• Development of IEEE 1500 interface to place the design in various test modes including the loopback mode. While working on this, I had learned various clock and reset synchronization mechanisms that are required as we move data between different asynchronous clock domains.
• Synthesis, Scan insertion, ATPG pattern generation, and validation of the ATPG patterns with sdf/timing information.
• Integrating an external BIST engine with DDR IP, so as to perform loopback test. The challenges here involved:
• o Conversion of data format between BIST engine and DDR IP taking into consideration the clock speeds of these IP's ( DDR, BIST )
• o Separation of data at both pos and neg edges of the clock from DDR to BIST
• Loopback pattern generation using the tool/flow developed earlier.

Jan 2011 – Feb 2012 · 1 yr 1 mo · Bengaluru Area, India

• Worked on Test and DFT aspects of c014.p ( CMOS process, higher performance , 45 nm ) DDR PHY. This includes:
• Development of IEEE 1500 RTL to be able to place the design in various test modes. These include:
• o Serial intest and extest modes
• o Parallel intest and extest modes
• o Functional loopback test mode
• Structured ATPG test for serial / parallel , intest / extest modes. This includes:
• o ATPG pattern generation and validation for each of the above modes
• o Understanding the test coverage in each of the modes and ways to improve the same
• o Mapping the patterns at IP level to SoC level using the serial test interface methodology and validating the same.
• Loop back tests with the help of a BIST engine to simulate the functional use scenario of the IP. In this mode we control the inputs through 1500, and observe the BIST outputs which again is made possible by 1500.
• Boundary Scan logic implementation
• Development of a flow to generate correct by construct test patterns for performing the loopback test.

Jan 2003 – Dec 2010 · 7 yrs 11 mos · Bengaluru Area, India

• As a DFT CAD Engineer, I was involved in development of various methodologies / tools / flows, which help the Test / Verification / DFT engineer to perform test execution on real designs. Following is a brief overview of the activities performed during this time period:
• Developed a flow around pBIST IP. pBIST is TI proprietary IP for performing programmable memory test for on chip memories. This flow is being developed in Perl. This includes:
• o Memory Test Algorithms - Writing memory test algorithms in assembly language, which the pBIST hardware IP understands.
• o pBISTTDLGen -Auto Generation of memory test patterns based on the memory, and algorithm specified by the user in excel interface.
• o pbistRomImageGen - Generation of pbist instruction rom which will enable to perform automatic memory test on all the memories available based on configuration inputs given by user.
• Developed the 'TI Memory Repair Flow' called as memConfig flow, which ensures the correctness and completeness of memory test data, and eases memory repair at Tester.
• Developed an excel based pattern generation flow for IEEE 1149.1, and 1500 standards. This software can be used to generate test patterns for any SoC/IP following JTAG / IEEE_1500 standard. It is successfully being used by various IP which include : FuseFarm, and DDR.

Mar 2000 – Dec 2002 · 2 yrs 9 mos · Bengaluru Area, India

• I had worked on various tools and flows which are built around TDL Language. TDL stands for Test Description Language. TDL is a TI proprietary language for specifying test and test vector data for VLSI designs in a tester independent format. Quick overview of work involved:
• 1. Worked on the TDL Parser, which provides API for the TDL language. The parser is implemented using flex, byacc and C++( SLOC: 23638 ). Work involved support and enhancements.
• 2. Worked on Functional TDL generation tool, called TDLGen. TDLGen helps customers in generating functional test patterns. This tool is again implemented using flex, byacc, and C++ ( SLOC: 19031 ).
• 3. Developed the iDFT ( integrated Design For Test ) flow. IDFT Flow is basically creating an automated flow around the Divide and Conquer Methodology of chip testing starting from DFT Insertion to Test Vector handoff ( dftInsertion -> ATPG -> Simulation -> handoff ). This tool is implemented in Perl ( SLOC : 14091 )
• 4. Worked on TDLUtils Framework. This framework provides an higher level of abstraction, over the existing TDL parser. This is implemented in Perl language, even though the underlying parser is implemented in C++. SWIG wrappers are used to interface between Perl and C++.