RAJKUMAR U

Software Engineer

Hyderabad, Telangana, India14 yrs 11 mos experience

Highly Stable

Key Highlights

Expertise in FPGA design and implementation.
Extensive experience with high-speed protocols.
Proficient in RTL design and verification.

Stackforce AI infers this person is a FPGA Design Engineer with expertise in high-speed communication protocols.

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Skills

Core Skills

Rtl DesignHardware ArchitectureVerificationFpga DesignTestingUsb ProtocolSmart Card TechnologyProtocol Development

Other Skills

Project PlanDesign Architecture SpecificationRTL CodingRTL IntegrationDesign SpecificationMicro-ArchitectureDevice identificationDesignImplementationFPGA implementationUSB HSIC TesterUTMISDRAM memory controllerPCIE PIPE Endpoint coreSmart card prototype

About

Expertise in logic design, simulation & implementation of FPGA based systems. Extensive knowledge of Xilinx devices, tools and IP cores. Hardware design experience with high speed protocols like PCIe, USB, DDR memory and MIPI. Specialties: PCI Express, USB, MIPI, Interlaken RTL logic design, simulation and verification DDR Memory Controller, UTMI PHY Verilog,VHDL, PERL Xilinx ISE & EDK, ChipscopePro, ModelSim, VERDI, Spyglass Oscilloscpe, Logic Analyzer Having valid B1 Visa upto 2020

Experience

14 yrs 11 mos

Total Experience

2 yrs 5 mos

Average Tenure

Current Experience

Amd

Staff Design Application Engineer

Feb 2022 – Feb 2022 · 0 mo · Hyderabad, Telangana, India

Xilinx

Staff Design Application Engineer

Jan 2022 – Feb 2022 · 1 mo · Hyderabad, Telangana, India

Infinera

Engineering Contractor

Dec 2020 – Nov 2021 · 11 mos · Bengaluru, Karnataka, India

Smartsoc solutions pvt ltd

Senior Lead - FPGA Design

Nov 2018 – Nov 2020 · 2 yrs · Bengaluru Area, India

Einfochips

2 roles

Member Technical Staff

Promoted

Jul 2014 – Oct 2018 · 4 yrs 3 mos

Project Plan
Design Architecture Specification
RTL Coding
RTL Integration

Project PlanDesign Architecture SpecificationRTL CodingRTL IntegrationRTL designHardware Architecture

Senior Engineer

Aug 2013 – Jun 2014 · 10 mos

RTL Coding
RTL Integration
Helping the Verification team to validate the testcases

RTL CodingRTL IntegrationVerificationRTL design

Mcci interconnect solutions pvt ltd

2 roles

Team Leader

Jul 2012 – Aug 2013 · 1 yr 1 mo · Chennai

Lead a team in FPGA Design and Verification
Design Specification to Micro-Architecture
RTL Coding to bitfile generation
Verification Environment Setup
Verification Plan/Test Plan Creation
Design Validation on the board

FPGA DesignVerificationDesign SpecificationMicro-Architecture

Senior Software Engineer

May 2010 – Feb 2012 · 1 yr 9 mos

Involved in the FPGA implementation of a USB HSIC Tester.
Implementation of UTMI which features data serialization and deserialization, bit stuffing and clock recovery and synchronization.
Implementation data selection logic and FIFO for clock crossing.
Integrating the SDRAM memory controller and PCIE PIPE Endpoint core to the Protocol data capture module.
Design Test cases for the protocol verification
Test scenario generation with compliance to the USB 2.0

FPGA implementationUSB HSIC TesterUTMISDRAM memory controllerPCIE PIPE Endpoint coreFPGA Design+1

Srm technologies

Senior System Analyst

Feb 2012 – Jul 2012 · 5 mos · Chennai Area, India

Involved in Device identification, Design, Implementation and Testing of FPGA/CPLD implementations

Device identificationDesignImplementationTestingFPGA Design

Acme technologies pvt ltd

3 roles

Senior Software Engineer

Promoted

Feb 2007 – Apr 2010 · 3 yrs 2 mos

Involved in the FPGA implementation of a Hi-speed Smart card prototype development from design to PAR. Analyzed the requirements for the card speed acceleration. Involved in the Low Level Design of hardware components.
Involved in the implementation of dynamic UART and RF front end for two different smart card protocol Standards ("B" and "C").
Involved in the implementation of DES algorithm and Random number generation for the card authentication.
Designed the Test cases for the protocol verification and the generation of test scenario with compliance to the ISO/IEC 10373-6.

FPGA implementationSmart card prototypeDynamic UARTRF front endDES algorithmFPGA Design+1

Software Engineer

Jan 2006 – Jan 2007 · 1 yr

Involved in the FPGA implementation of a prototype for an on-chip debugger interface for an 8 bit RISC processor. Analyzed the requirements for the Proprietary protocol. Involved in the Low Level Design of hardware components, implementation of Proprietary protocol in FPGA from design to PAR and developed test cases for the protocol verification.
Involved in the FPGA implementation of a prototype for a flash writer for an 8 bit RISC processor. Analyzed the requirements for the Proprietary protocol. Involved in the Low Level Design of hardware components, implementation of Proprietary protocol in FPGA from design to PAR.
Involved in the hardware testing of dual SIM interface (SIMIF) evaluation board. Captured the parameter data’s of the SIM in the oscilloscope. Verified the parameters with the ATR of the SIM.
Involved in the FPGA implementation of crypto-algorithms such as DES, AES and communication protocols (UART) for the IP development.
Involved in the development of an excel VBA application for the automated top module generator and an UCF generator. Devised test specifications to check the application for the defect fix.

FPGA implementationProprietary protocolCrypto-algorithmsVBA applicationFPGA DesignProtocol Development

Software Engineer Trainee

Aug 2005 – Jan 2006 · 5 mos

Underwent training in personal software process, STARC coding practices, testing methodologies and using revision control systems.This training helps to Improve their estimating and planning skills, Make commitments that we can keep, Manage the quality of the projects and Reduce the number of defects in the work.