Rohit lakkaraju

Software Engineer

Bengaluru, Karnataka, India15 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Timing Closure and Static Timing Analysis.
  • Strong background in VLSI Engineering from a prestigious institution.
  • Proven track record in the wireless industry.
Stackforce AI infers this person is a Senior Design Engineer specializing in VLSI and ASIC design within the wireless industry.

Contact

LinkedIn

Skills

Other Skills

Static Timing AnalysisVLSIVerilogSystemVerilogASICTCLTiming ClosureSoCPrimetimeOpen Verification MethodologyIntegrated Circuit DesignDRCLogic SynthesisFloorplanningClock Tree Synthesis

About

Experienced Senior Design Engineer with a demonstrated history of working in the wireless industry. Skilled in Timing Closure, Design Rule Checking (DRC), Clock Tree Synthesis, Primetime, and Verilog. Strong engineering professional with a MS focused in VLSI Engineering from veda iit.

Experience

15 yrs 8 mos
Total Experience
2 yrs 7 mos
Average Tenure
9 yrs 5 mos
Current Experience

Qualcomm

3 roles

Staff Engineer

Dec 2021 – Present · 4 yrs 5 mos

Sr Lead Engineer

Promoted

Dec 2019 – Oct 2022 · 2 yrs 10 mos

Senior Design Engineer

Dec 2016 – Dec 2019 · 3 yrs

Hcl technologies

Lead Engineer

Oct 2015 – Nov 2016 · 1 yr 1 mo · Bengaluru Area, India

Concept2silicon systems

ASIC Physical design engineer

Apr 2015 – Oct 2015 · 6 mos · Bengaluru Area, India

Xilinx

Software Engineer

Nov 2013 – Apr 2015 · 1 yr 5 mos · Hyderabad Area, India

Soctronics

2 roles

Physical Design Engineer

Jul 2012 – Oct 2013 · 1 yr 3 mos · Hyderabad Area, India

Intern Physical design engineer

Jul 2011 – Jul 2012 · 1 yr · Hyderabad Area, India

Servomax india limited

assistant engineer automation

Jun 2009 – Jun 2010 · 1 yr

Education

veda iit

MS — VLSI Engineering

Jan 2010 – Jan 2012

Holymary institue of technology and sciences

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2005 – Jan 2009

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