Sachin Jain — Software Engineer
Semiconductor Industry | Expertise in Clock & Reset Domain Crossing Methodology | Working on VLSI FrontEnd TFMs | Verilog, SystemVerilog, Perl, Python, TCL | SpyGlass, VC-Static, VCS, Questa, Design Compiler, Fusion complier | Project Dashboards development | Learning Mixed Signal Design TFMs Strong engineering professional with a Master of Technology (M.Tech.) specialisation in VLSI Design from Nirma University & Bachelor of Technology (B.Tech.) in Electronics and Communication Engineering from Indus University.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in digital design methodologies.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 1 mo
Skills
- Design Methodology
- Digital Design
- Scripting
- Front-end Flow Development
Career Highlights
- Expertise in VLSI Design and Methodologies
- Proven track record in tool flow innovation
- Strong leadership in cross-functional teams
Work Experience
Intel Corporation
Logic Design Methodology Engineer (9 mos)
Engineering Manager (5 mos)
Logic Design Methodology Engineer (3 yrs)
Computer Aided Design Design Engineer (3 yrs 6 mos)
Intern (11 mos)
ESYNC Student Association
General Seceratary (1 yr 6 mos)
Citizens for Accountable Governance
Team Member (0 mo)
ROBOSAPIENS TECHNOLOGIES Pvt. Ltd.
Intern (1 mo)
Education
Master’s Degree at Nirma University
Bachelor of Technology (BTech) at Indus University , Ahmedabad
High School at Infocity Junior Science College,Gandhinagar
Secondary Education at Sakar English School