Saurabh Deswal

Software Engineer

Bengaluru, Karnataka, India9 yrs 11 mos experience

Highly Stable

Key Highlights

9+ years in design verification across major tech companies.
Expert in UVM and Verilog-based testbench development.
Achieved zero post-silicon bugs in production.

Stackforce AI infers this person is a Design Verification Engineer specializing in semiconductor and mixed signal ASIC verification.

Contact

Skills

Core Skills

Design VerificationTestbench DevelopmentFunctional VerificationPerformance VerificationMixed Signal Verification

Other Skills

VerilogCC++UVMRTLTest MethodologiesMixed Signal ASICsMatlabSystemVerilogPythonModelSimVHDLKeilProteusXilinx ISE

About

Design Verification Engineer with 9+ years of experience across consumer silicon, mixed signal ASICs, and RISC-V based architectures. Skilled in building UVM and Verilog-based testbenches from scratch, with hands-on experience in functional, performance, and mixed signal verification. Have worked across the stack — from audio ASICs at Cirrus Logic to memory controllers and media hardware at Apple. Passionate about catching bugs before silicon and building robust verification infrastructure that scales.

Experience

9 yrs 11 mos

Total Experience

3 yrs 2 mos

Average Tenure

5 mos

Current Experience

Rivos inc.

2 roles

Design Verification Engineer

Dec 2022 – Jan 2026 · 3 yrs 1 mo

Design Verification Engineer

Aug 2022 – Dec 2022 · 4 mos

Built the IO Cache verification testbench from scratch using Verilog transactors with checkers written in C/C++, resulting in zero post-silicon bugs found in production
Designed and structured the testbench architecture independently, covering end-to-end functional scenarios and ensuring thorough coverage across IO cache operations

VerilogCC++Design VerificationTestbench Development

Apple

Design Verification Engineer

Mar 2020 – Aug 2022 · 2 yrs 5 mos · Austin, Texas, United States

Built and maintained performance verification for the Memory Controller subsystem by developing end-to-end UVM scoreboards and directed tests, enabling accurate RTL-to-model correlation using performance team traces
Worked on functional verification of key media processing hardware including Apple’s Video Engine, driving coverage closure through constrained-random and directed test methodologies

UVMRTLPerformance VerificationFunctional Verification

Cirrus logic

Design Verification Engineer

Jul 2016 – Mar 2020 · 3 yrs 8 mos · Austin, Texas Metropolitan Area

Developed UVM testbenches for Mixed Signal ASICs — including constrained-random tests, bit-accurate scoreboards, and functional coverage models — achieving 100% code and functional coverage targets
Wrote Matlab scripts to compute group delay across Digital/Mixed Signal SOC blocks and integrated the analysis into the existing UVM TB infrastructure

UVMMixed Signal ASICsMatlabDesign VerificationMixed Signal Verification