Shashi Kanth Kondaparthi

Software Engineer

Hyderabad, Telangana, India18 yrs 1 mo experience
Highly Stable

Key Highlights

  • 18+ years in Physical Design domain.
  • Expertise in multiple technology nodes down to 3nm.
  • Led 13 Tapeouts with significant component blocks.
Stackforce AI infers this person is a VLSI Physical Design Engineer with extensive experience in semiconductor technology.

Contact

LinkedIn

Skills

Core Skills

Very-large-scale Integration (vlsi)Design For Manufacturing

Other Skills

Floor planningPower PlanningPlacementClock Tree SynthesisOptimizations after CTS & RoutingCongestion AnalysisRoutingRC ExtractionTiming AnalysisECOsLow Power techniquesLEC analysisDRC-LVS fixingDFMBudgeting/SDC-delivery

About

Total experience of 18+ years in Physical Design domain, with 13 Tapeouts and some revision Tapeouts from Floorplan-to-Tapeout on 90nm, 80nm, 65nm, 45nm, 32nm & 28nm, 14nm, 12nm, 7nm, 6nm/5nm, 3nm TSMC G+/LP & GF Processes, with 300K-1.2M component blocks in all projects.

Experience

18 yrs 1 mo
Total Experience
9 yrs
Average Tenure
--
Current Experience

Amd

Member of Technical Staff

Oct 2007 – Nov 2023 · 16 yrs 1 mo · Hyderabad, Telangana, India · Hybrid

  • Member of Technical Staff: Aug 2021 to Nov 2023
  • Section Manager: Aug 2018 to July 2021
  • Member of Technical Staff: Aug 2013 to July 2018
  • Senior Design Engineer: Aug 2010 to July 2013
  • ASIC Design Engineer: Oct 2007 to July 2010
  • On-Site experience at AMD, Sunnyvale, USA: Aug 2008 to Nov 2008
  • Detailed Areas of Experience in the PD Flow
  • Floor planning, Power Planning, Placement, Clock Tree Synthesis, Optimizations after CTS &
  • Routing, Congestion Analysis, Routing, RC Extraction, Timing Analysis, ECOs, Low Power
  • techniques, LEC analysis, DRC-LVS fixing, DFM, Budgeting/SDC-delivery, FCT-DRV analysis/fixes,
  • Dynamic IR & SigEM analysis/fixes.
  • Hands on Experience on Tools
  • SOC Encounter, IC Compiler, Sierra pinnacle, StarRC, PrimeTime, Calibre, Conformal, Formality.
Very-Large-Scale Integration (VLSI)Design for ManufacturingFloor planningPower PlanningPlacementClock Tree Synthesis+21

Gd micro systems pvt. ltd

Place & Route Engineer

Jan 2005 – Jan 2007 · 2 yrs · Hyderabad, Telangana, India · On-site

  • As a Place & Route Engineer completed one ECO Project in 80nm & one P&R project in 65nm.
Very-Large-Scale Integration (VLSI)Design for Manufacturing

Education

VEDA IIT-JNTUH, HYDERABAD

Master's degree — VLSI CHIP DESIGNING

Jan 2003 – Jan 2005

Visvesvaraya Technological University, Belgaum

Bachelor of Engineering - BE

Jan 1998 – Jan 2002

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