Shruti Dutta

DevOps Engineer

Santa Clara, California, United States8 yrs 6 mos experience

Most Likely To Switch

Key Highlights

4+ years in design verification at top tech companies
Expertise in CPU and Video hardware verification
Strong academic background with a 3.96 GPA in MS ECE

Stackforce AI infers this person is a Design Verification Engineer with expertise in CPU and Video hardware industries.

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Skills

Core Skills

Design VerificationCpu VerificationCache MicroarchitectureResearchVerificationDesign

Other Skills

VerilogSystem VerilogUVMDigital ElectronicsAlgorithmsAssertion GenerationTestbench AutomationVerification IPUSB ProtocolSRAM DesignC++HTMLMicrosoft OfficeJavaMicrosoft Word

About

Industrial experience of around 4+ years in design verification with exposure to IP Block/Top level verification including test-plan mapping, functional coverage, writing SV assertions. Skills : C, Verilog, System Verilog,UVM( methodology) Interests in Computer Architecture and modern processors

Experience

8 yrs 6 mos

Total Experience

1 yr 3 mos

Average Tenure

1 yr 7 mos

Current Experience

Nvidia

Senior CPU Design Verification Engineer

Nov 2024 – Present · 1 yr 7 mos · Santa Clara, California, United States · Hybrid

Working on unit L2 CPU verification

VerilogSystem VerilogUVMDigital ElectronicsDesign VerificationCPU Verification

Apple

2 roles

CPU Design Engineer 3

Jun 2023 – Nov 2024 · 1 yr 5 mos · United States · On-site

Last Level Cache microarchitecture and design verification

VerilogSystem VerilogUVMDigital ElectronicsDesign VerificationCache Microarchitecture

Hardware Engineering Intern

May 2022 – Aug 2022 · 3 mos · San Diego, California, United States

worked on automating assertion generation for the Wireless Radio IP to ease the process of manually adding design assertions to the testbench

Assertion GenerationTestbench AutomationDesign Verification

The university of texas at austin

2 roles

Research Assistant

Jan 2022 – Jun 2023 · 1 yr 5 mos

Exploring the possible implementation of Novel Error Correcting Codes to cater to reliability demands of smaller memory structures under the guidance of Prof. Nur Touba. Funded by NSF grant.

ResearchAlgorithms

Research Assistant

Sep 2021 – Jan 2022 · 4 mos

Research Assistant for Prof. Andrew Brodsky in the domain of organizational behaviour

Qualcomm

Senior Video HW Design Verification Engineer

Oct 2020 – Aug 2021 · 10 mos · Bengaluru, Karnataka, India

a) Part of Video Hardware and DV Team
b) Participating in Block and Top level verification for Video core
c) Verifying Video Decoding and Encoding RTL modules for codecs av1d, h265d,h265e and mpeg2d using SV random testbench

VerilogSystem VerilogUVMDesign Verification