Suman Pachimatla

Software Engineer

Bengaluru, Karnataka, India11 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI physical design and verification.
Proven track record with leading semiconductor companies.
Strong academic background in VLSI systems.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Physical Design.

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Skills

Core Skills

Physical DesignCmosVlsi

Other Skills

Place & RouteIntegrated Circuits (IC)VLSI-Physical VerificationDRCLVSECOsSynopsys ICC & ICC2Calibre toolsInnovus toolsIC CompilerIC ValidatorDigital ElectronicsLogic DesignStatic Timing AnalysisCircuit Design

About

Experienced SoC Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Place & Route, Integrated Circuits (IC), Design Rule Checking (DRC), and CMOS. Strong engineering professional with a Master of Technology (M.Tech.) focused in VLSI systems from National Institute of Technology Tiruchirappalli.

Experience

11 yrs 3 mos

Total Experience

2 yrs 9 mos

Average Tenure

5 yrs 8 mos

Current Experience

Intel corporation

SoC Design Engineer

Sep 2020 – Present · 5 yrs 8 mos · Bengaluru, Karnataka, India · Remote

Physical DesignPlace & RouteCMOSIntegrated Circuits (IC)

Lakshsemi

Senior Physical Design Engineer

Sep 2017 – Aug 2020 · 2 yrs 11 mos · Bengaluru, Karnataka, India

Mindlance technologies

Physical Design Engineer

Jul 2016 – Aug 2017 · 1 yr 1 mo · Bangalore, India

 Having 2 years, 8 Months of work experience as an Engineer in VLSI-Physical Verification.
 Currently working as a Physical design Engineer II at Qualcomm India Pvt Ltd as a client.
 Experience in owning multiple projects ( 14nm and 10nm) with Intel, TSMC and Samsung foundries
 Worked as a Partition owner - Owning the critical Partitions and implementing Timing and Functional ECOs like Buffer insertion, Net Improvement, Net degradation and Cell Sizes.
 Experiences in fixing the violations - DRC, ERC, PERC, LVS, Antenna violations, Soft check and Extraction checks.
 Hands on experience in Tools: Synopsys ICC & ICC2, IC workbench, Calibre tools, Innovus tools

VLSI-Physical VerificationDRCLVSECOsSynopsys ICC & ICC2Calibre tools+3

Intel corporation

Physical Design Engineer

Nov 2014 – Jun 2016 · 1 yr 7 mos · Bengaluru, Karnataka, India

Working on 14 nm Intel specific SOC Physical Verification flow.
Good Knowledge on physical design tools like IC Compiler, IC Validator.
Knowledge on full PnR flow, responsibilities were doing project Setup, floor planning, macro placement, Power planning, Power Routing, Placement and Routing.
Implemented ECO’s with less effect of DRCs and LVS errors
Hands on Experience of adding buffers, improving net by rerouting and Fix LVS & DRC issues for layout cells that had edits in the schematics. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks
Good knowledge on Latch up, EM, IR Drop, Antenna effect and Density fixing.
Good Knowledge on physical design tools like IC Compiler, IC Validator.
Acquainted with projects in Physical Verification at Block level.